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Computer Architecture and System Laboratory

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1) 2)

期刊論文發表

  1. Ching-Wen Lin and Chung-Ho Chen,
    A Processor and Cache Online Self-Testing Methodology for OS-Managed Platform,
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
    Vol. 25, No. 8, pp. 2346-2359, August 2017.

  2. En-Hao Chang, Chen-Chieh Wang, Chien-Te Liu, Kuan-Chung Chen and Chung-Ho Chen,
    Virtualization Technology for TCP/IP Offload Engine,
    IEEE Transactions on Cloud Computing,
    Vol. 2, No. 2, April-June 2014. (SCI, EI)

  3. Chen-Chieh Wang and Chung-Ho Chen,
    A System‐Level Network Virtual Platform for IPsec Processor Development,
    IEICE Transactions on Information and Systems,
    Vol.E96-D, No.5, pp.1095-1104, May 2013. (SCI, EI)

  4. Yi-Ying Tsai and Chung-Ho Chen,
    Energy-efficient Trace Reuse Cache for Embedded Processor,
    IEEE Transactions on Very Large Scale Integration Systems,
    Vol. 19, No. 9, pp. 1681-1694, September 2011. (SCI, EI)

  5. Tai-Hua Lu, Chung-Ho Chen, and Kuen-Jong Lee,
    Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores,
    IEEE Transactions on Very Large Scale Integration Systems,
    Vol. 19, No. 3, pp. 516-520, March 2011. (SCI, EI)

  6. Wei-Cheng Lin and Chung-Ho Chen,
    Frame Buffer Access Reduction for MPEG Video Decoder,
    IEEE Transactions on Circuits and Systems for Video Technology,
    Vol. 18, No. 10, pp. 1452-1456, October 2008. (SCI, EI)

  7. Chung-Ming Chen and Chung-Ho Chen,
    Configurable VLSI Architecture for Deblocking Filter in H.264/AVC,
    IEEE Transactions on Very Large Scale Integration Systems,
    Vol. 16, No. 8, pp. 1072-1082, August 2008. (SCI, EI)

  8. Chung-Ming Chen and Chung-Ho Chen,
    Window Architecture for Deblocking Filter in H.264/AVC,
    International Journal of Innovative Computing, Information and Control,
    Vol. 3, No. 6, pp. 1677-1695, December 2007. (SCI, EI)

  9. Chung-Ho Chen and Kuo-Su Hsiao,
    Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality,
    IEEE Transactions on Computers,
    Vol. 56, No. 11, pp. 1534-1548, November 2007. (SCI, EI)

  10. Chung-Ho Chen, Chao-Hsien Hsu, and Chen-Chieh Wang,
    Scalable IPv6 Lookup/Update Design for High-Throughput Routers,
    Journal of Internet Technology,
    Vol. 8, No. 3, pp. 261-269, July 2007. (EI)

  11. Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao,
    Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores,
    IEEE Transactions on Very Large Scale Integration Systems,
    Vol. 15, No. 5, pp. 505-517, May 2007. (SCI, EI)

  12. Chung-Ming Chen and Chung-Ho Chen,
    An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC,
    IEICE Transactions on Information and Systems,
    Vol. E90-D, No.1 pp.99-107, January 2007. (SCI, EI)

  13. Kuo-Su Hsiao and Chung-Ho Chen,
    Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation,
    IEEE Transactions on Very Large Scale Integration Systems,
    Vol. 14, No. 10, pp. 1089-1102, October 2006. (SCI, EI)

  14. M.-D. Shieh, M.-H. Sheu, C.-H. Chen , and H.-F. Lo,
    A Systematic Approach for Parallel CRC Computations,
    Journal of Information Science and Engineering,
    Vol. 17, No. 3, pp. 445-461, May 2001. (SCI)

  15. C.-H. Chen and Akida Wu,
    Address Prediction Using a Bit-Matrix Indexing Scheme for Selective Update,
    Journal of Computers,
    Vol. 12 No.3, September 2000.

  16. C.-H. Chen and Akida Wu,
    Performance Evaluation of Load/Store Issue and Memory Access Policies,
    Journal of the Chinese Institute of Engineers,
    Vol.23, No. 6, pp. 697-709, 2000. (SCI, EI)


會議論文發表

  1. J.-W. Lin , and Chung-Ho Chen,
    Processor Shield for L1 Data Cache Software-Based On-line Self-testing,
    in Asia South Pacific Des. Autom. Conf. ,
    January 16-19, 2017, Japan

  2. J.-W. Lin , and Chung-Ho Chen,
    A Processor Shield for Software-Based On-Line Self-Test,
    in IEEE Asia Pacific Conf. Circuits and Systems,
    October 25-28, 2016, Korea

  3. Yun-Chi Huang, Kuan-Chieh Hsu, Wan-shan Hsieh, Chen-Chieh Wang, Chia-Han Lu, and Chung-Ho Chen_,
    Dynamic SIMD Re-convergence with Paired-Path Comparison ,
    in the 2016 IEEE International Symposium on Circuits and Systems (ISCAS),
    May 23-25, 2016, Montreal, Canada.

  4. Yung Hsu and Chung-Ho Chen,
    A Heterogeneous System Architecture Conformed GPU Platform Supporting OpenCL and OpenGL,
    Taiwan and Japan Conference on Circuits and Systems (TJCAS),
    Aug. 18-23, 2015, Japan

  5. Heng-Yi Chen, and Chung-Ho Chen,
    An HSAIL ISA Conformed GPU Platform,
    In International Conference on Innovation, Communication and Engineering (ICICE),
    Oct 23-28. 2015. Xiangtan, Hunan, P.R. China

  6. Chien-Hsuan Yen, Kuan-Chung Chen and Chung-Ho Chen,
    A memory-efficient NoC system for OpenCL many-core platform,
    in the 2015 IEEE International Symposium on Circuits and Systems (ISCAS),
    May 24-27, 2015, Lisbon, Portugal.

  7. Ching-Wen Lin and Chung-Ho Chen,
    Unambiguous I-cache testing using software-based self-testing methodology,
    in the 2014 IEEE International Symposium on Circuits and Systems (ISCAS),
    June 1-5, 2014 ,Melbourne VIC, Australian.

  8. Kuan-Chung Chen and Chung-Ho Chen,
    An OpenCL Runtime System for a Heterogeneous many-Core Virtual Platform ,
    in the 2014 IEEE International Symposium on Circuits and Systems (ISCAS),
    June 1-5, 2014 ,Melbourne VIC, Australian.

  9. Jhe-Yu Liou and Chung-Ho Chen,
    Re-visit Blocking Texture Cache Design for Modern GPU,
    in the 11th International SoC Design Conference (ISOCC),
    Nov. 3-6, 2014, Jeju, Korea.

  10. Tzu-Hsuan Hsu, Ching-Wen Lin and Chung-Ho Chen,
    Using Condition Flag Prediction to Improve the Performance of Out-of-Order Processors,
    in the IEEE International Symposium on Circuits and Systems (ISCAS),
    May 19-23, 2013 ,Beijing, China.

  11. Chien-Te Liu, Kuan-Chung Chen and Chung-Ho Chen,
    CASL Hypervisor and its Virtualization Platform,
    in the IEEE International Symposium on Circuits and Systems (ISCAS),
    May 19-23, 2013 ,Beijing, China.

  12. Hsu-Yao Huang, Chi-Yuan Huang, and Chung-Ho Chen,
    Tile-Based GPU Optimizations through ESL Full System Simulation,
    in the IEEE International Symposium on Circuits and Systems (ISCAS),
    May 20-23, 2012, Seoul, Korea.

  13. Chen-Chieh Wang, Sheng-Hsin Lo, Yao-Ning Liu, and Chung-Ho Chen,
    NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development,
    in the IEEE International Symposium on Circuits and Systems (ISCAS),
    May 20-23, 2012, Seoul, Korea.

  14. Chen-Chieh Wang and Chung-Ho Chen,
    An Optimized Cryptographic Processing Unit for IPsec Processors,
    in the 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC),
    June 19-22, 2011, Gyeongju, Korea.

  15. Kuan-Chung Chen and Chung-Ho Chen,
    A Synchronization Profiler for Hybrid Full System Simulation Platform,
    in the International SoC Design Conference (ISOCC-2010),
    Nov. 22-23, 2010, Incheon, Korea.

  16. Xie-Zeng Shen, Shin-Ying Lee, and Chung-Ho Chen,
    Full System Simulation with QEMU: an Approach to Multi-View 3D GPU Design,
    in the IEEE International Symposium on Circuits and Systems (ISCAS),
    May 30 - June 2, 2010, Paris, France.

  17. Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, and Kuen-Jong Lee,
    Full System Simulation and Verification Framework,
    in the Proceedings of the Fifth International Conference on Information Assurance and Security (IAS-2009),
    August 18-20, 2009, Xi'an, China.

  18. Chen-Chieh Wang, Ro-Pun Wong, Jing-Wun Lin, and Chung-Ho Chen,
    System-Level Development and Verification Framework for High-Performance System Accelerator,
    in the IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT),
    April 27-30, 2009, Hsinchu, Taiwan.

  19. Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen,
    A Software-Based Test Methodology for Direct-Mapped Data Cache,
    in the IEEE Seventeenth Asian Test Symposium (ATS), November 24-27, 2008, Sapporo, Japan.

  20. Wei-Cheng Lin and Chung-Ho Chen,
    Avoiding Unnecessary Frame Memory Access and Multi-Frame Motion Estimation Computation in H.264/AVC,
    in the IEEE International Symposium on Circuits and Systems (ISCAS), May 18-21, 2008, Seattle, Washington, USA.

  21. Tai-Hua Lu, Chung-Ho Chen, and Kuen-Jong Lee,
    A Hybrid Self-Testing methodology of Processor Cores,
    in the IEEE International Symposium on Circuits and Systems (ISCAS), May 18-21, 2008, Seattle, Washington, USA.

  22. Yi-Ying Tsai, Chia-Jung Hsu, and Chung-Ho Chen,
    Address Compression for Scalable Load/Store Queue Implementation,
    in the IEEE International Symposium on Circuits and Systems (ISCAS), May 18-21, 2008, Seattle, Washington, USA.

  23. Tai-Hua Lu, Chung-Ho Chen, and Kuen-Jong Lee,
    A Hybrid Software-Based Self-Testing methodology for Embedded Processor,
    in the ACM Symposium on Applied Computing (SAC), March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)

  24. Yi-Ying Tsai, Chia-Jung Hsu, and Chung-Ho Chen,
    Power-efficient and Scalable Load/Store Queue Design via Address Compression,
    in the ACM Symposium on Applied Computing (SAC), March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)

  25. Wei-Cheng Lin and Chung-Ho Chen,
    A Data-Reuse Scheme for Avoiding Unnecessary Frame Buffer Accesses and Display RAM Accesses in MPEG-4 ASP Video Decoder,
    in the IEEE International SoC Conference (SOCC), September 26-29, 2007, Hsinchu, Taiwan.

  26. Yi-Cheng Chung, Stanley Lee, and Chung-Ho Chen,
    A Packet Forwarding Method for the iSCSI Virtualization Switch,
    in the 4th International Workshop on Storage Network Architecture and Parallel I/Os (SNAPI), September 24, 2007, San Diego, California, USA.

  27. Wei-Cheng Lin and Chung-Ho Chen,
    Reduction of Frame Memory Accesses and Motion Estimation Computations in MPEG-4 Video Encoder,
    in the 16th International Conference on Computer Communications and Networks (ICCCN), August 13-16, 2007, Honolulu, Hawaii, USA.

  28. Chung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, and Han-Chiang Chen,
    Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator,
    in the 31st Annual IEEE Conference on Local Computer Networks (LCN), November 14-16, 2006, Tampa, Florida, USA.

  29. Kuo-Su Hsiao and Chung-Ho Chen,
    Scheduler Optimization by Exploring Wakeup Locality,
    in the International Conference of Computer Engineering & Systems (ICCES), November 5-7, 2006, Egypt.

  30. Chung-Ming Chen, Chung-Ho Chen, Jian-Ping Zeng, and Chao-Tang Yu,
    Windows Processing for Deblocking Filter in H.264/AVC,
    in the Proceeding of the 32nd Annual Conference of the IEEE Industrial Electronics (IECON), November 7-10, 2006, Paris, France.

  31. Kuo-Su Hsiao and Chung-Ho Chen,
    Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling,
    in the International Conference of Computer Design, October, 2006, USA. (EI)

  32. Wei-Cheng Lin and Chung-Ho Chen,
    Exploring Reusable Frame Buffer Data for MPEG-4 Video Decoding,
    in the IEEE International Symposium on Circuits and Systems (ISCAS), 2006, Island of Kos, Greece. (EI)

  33. Chung-Ming Chen, Jian-Ping Zeng, Chung-Ho Chen, Chao-Tang Yu, and Yu-Pin Chang,
    Window Architecture for Deblocking Filter in H.264/AVC,
    in the 6th IEEE International Symposium on Signal Processing and Information Technology, August 27-30, 2006, Vancouver, Canada. (EI)

  34. Yi-Ying Tsai, Ke-Jia Lee, and Chung-Ho Chen,
    Code Compression Architecture for Memory Bandwidth Optimization in Embedded Systems,
    in the Proceeding of the International Computer Symposium (ICS), 2006, Taiwan.

  35. Po-Kai Chan, Chung-Ho Chen, and Cheng-Yeh Yu,
    An iWARP-Based TCP/IP Offload Engine,
    in the Proceeding of the 17th VLSI Design/CAD Symposium, August 8-11, 2006.

  36. Kuo-Su Hsiao and Chung-Ho Chen,
    An Efficient Wakeup Design for Energy Reduction in High-Performance Superscalar Processors,
    in the ACM SIGMicro International Conference on Computing Frontiers (CF), 2005, Italy. (EI)

  37. Chung-Ming Chen and Chung-Ho Chen,
    A Memory Efficient Architecture for Deblocking Filter in H.264 Using Vertical Processing Order,
    in the IEEE International Conference on Intelligent Sensors, Sensor Networks, and Information Processing (ISSNIP), 2005, Australia.

  38. Chung-Ming Chen and Chung-Ho Chen,
    Parallel Processing for Deblocking Filter in H.264/AVC,
    in the International Conference on Communications, Internet and Information Technology (CIIT), 2005, Cambridge, USA. (EI)

  39. Chung-Ming Chen and Chung-Ho Chen,
    Alternative Processing Order with Efficient Architecture for Adaptive Deblocking Filter in H.264/AVC,
    in the International Conference on Communications, Internet, and Information Technology (CIIT), 2005, Cambridge, USA. (EI)

  40. Chung-Ming Chen and Chung-Ho Chen,
    An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding,
    in the International Conference on Computer Graphics and Imaging (CGIM), 2005, Honolulu, Hawaii, USA. (EI)

  41. Chung-Ming Chen and Chung-Ho Chen,
    An Efficient VLSI Architecture for Edge Filtering in H.264/AVC,
    in the International Conference on Circuits, Signals, and Systems, 2005, Marina del Rey, CA, USA.

  42. F.-M Huang and C.-H. Chen,
    Memory Access Scheduling and Bank Precharge Strategies,
    in the poster proceeding of 12 th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 2004, Netherlands.

  43. Wei-Cheng Lin and Chung-Ho Chen,
    An Energy-Delay Efficient Power Management Scheme for Embedded System in Multimedia Applications,
    in Proceedings of The IEEE Asia Pacific Conference on Circuit & System (APCCAS),2004, Taiwan. (EI)

  44. N.-Y. Ker, and C.-H. Chen,
    An Effective SDRAM Power Mode Management Scheme for Performance and Energy Sensitive Embedded Systems,
    in the Proceeding of Asia and South Pacific Design Automation Conference (ASP-DAC), 2003, Japan.

  45. W.-Z. Lin, and C.-H. Chen,
    10/100/1000 Mbps Ethernet MAC with Clock Management for AMBA System,
    in the Proceeding of the 13th VLSI Design/CAD Symposium, 2002.

  46. 盧偉聖、陳中和、蔡宜穎、林宇峰,
    The Design of a Digital Control Technology for Lighting and Special Effects,
    in the Proceeding of Taiwan Power Electronic Conference, 2002.

  47. C.-H. Chen, M.-D. Shieh, and Jimmy Shou,
    VLSI Architecture of an Instruction-Based Crypto Coprocessor,
    in the Proceeding of the 11th VLSI Design/CAD Symposium, 2000.

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