計算機架構與系統實驗室

Computer Architecture and System Laboratory

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member:advisor

陳中和教授

學歷

  • 華盛頓大學電機博士(1993)
    Ph.D., University of Washington, Seattle, U.S.A.
  • 密蘇里-羅拉大學電機碩士 (1989)
    M.S., University of Missouri-Rolla, U.S.A.
  • 國立台北工專 - 72年5電5甲 (1983)
    National Taipei Institute of Technology, R.O.C.


主要經歷

  • 國際電機電子工程師學會中華民國第一分會常務理事 (Since 2012)
  • IEEE Circuit and System Society Tainan Chapter Chair (Since 2011)
  • 國立成功大學電機系教授(2006~)
    Professor, Department of Electrical Engineering,
    National Cheng-Kung University
  • 國立成功大學電機系副教授(1999~2006)
    Associate Professor, Department of Electrical Engineering,
    National Cheng-Kung University
  • 國立雲林科技大學電子系副教授 (1997~1999)
    Associate Professor, Department of Electronic Engineering,
    National Yunlin University of Science and Technology
  • 國立雲林技術學院電子系副教授(1993~1997)
    Associate Professor, Department of Electronic Engineering,
    National Yunlin Institute of Technology
  • 華盛頓大學電機系研究助理 (1989~1993)
    Research Assistant, Department of Electrical Engineering,
    University of Washington
  • 台灣飛利浦電子工程師 (1986~1987)
    Engineer, Philips Electronics, Inc. Taiwan


學門專長

  • 計算機架構
    Computer Architecture
  • SOC 整合
    SOC Integration
  • VLSI 晶片設計
    VLSI Chip Design
  • 多重處理器系統
    Multiprocessor Systems
  • 資料網路
    Data Network
  • 微算機系統設計
    Microprocessor System Design
  • 容錯處理系統
    Fault-tolerant Computing System


特殊榮譽

  1. 2013 年, 2013 IEEE Circuits and Systems Society Region 10 Chapter of the Year Award

  2. 2012 年, 陳中和 教授榮獲 國立成功大學 「 101學年度 教學優良教師獎 」。

  3. 2009 年, 陳中和 教授榮獲國立成功大學「教學傑出教師獎 」。

  4. 2009 年, 陳中和 教授指導學生 江定遠、黃煦堯 參加教育部九十七學年度全國大學校院積體電路設計競賽,榮獲 大學部標準元件數位電路設計組 優等

  5. 2007 年, 陳中和 教授指導學生 盧泰樺、蔡宜穎、林奕成、林璟汶 參加第七屆旺宏金矽獎半導體設計與應用大賽,全國各大學第一顆經由 Linux 驗證之 ARM ISA-like 管線化處理器 榮獲 優勝獎

  6. 2006 年, 陳中和 教授指導學生實作功能齊全之 ARM9 相容處理器,Booting Linux 作業系統成功運轉,第一顆成大電機系、電通所、電資學院的全功能一般用途處理器。

  7. 2005 年, 陳中和 教授指導學生 詹博凱、余承燁 參加第三屆 Altera Nios 嵌入式處理器設計大賽,TCP/IP Offload Engine (TOE) for SOC System 榮獲 季軍

  8. 2003 年, 陳中和 教授指導學生 許照賢、余承燁、陳漢威、熊恂緯 參加教育部九十一學年度大學院校矽智產 SIP設計競賽,榮獲 研究所 Soft IP 組 佳作
    台顧字第 0 九二 00 九八九九五號。

  9. 2000 年, 陳中和 教授指導學生參加教育部八十八學年度大學院校矽智產 SIP設計競賽,
    榮獲 研究所 FPGA 印證 特優獎
    榮獲 研究所 Soft IP 組 優等獎
    台 ( 八九 ) 顧字第八九 0 九三九二三號。

  10. 1999 年, 陳中和 教授指導學生參加教育部八十七學年度大學院校矽智產 SIP設計競賽,榮獲 大學部 Soft IP 組 特優獎
    台 ( 八八 ) 顧字第八八 0 九一七二六號。


期刊論文

IEEE/ACM Transactions 期刊論文 (13)

  1. En-Hao Chang, Chen-Chieh Wang, Chien-Te Liu, Kuan-Chung Chen and Chung-Ho Chen,
    Virtualization Technology for TCP/IP Offload Engine,
    IEEE Transactions on Cloud Computing,
    Vol. 2, No. 2, April-June 2014. (SCI, EI)

  2. Yi-Ying Tsai and Chung-Ho Chen,
    Energy-efficient Trace Reuse Cache for Embedded Processor,
    IEEE Transactions on Very Large Scale Integration Systems,
    Vol. 19, No. 9, pp. 1681-1694, September 2011. (SCI, EI)

  3. Tai-Hua Lu, Chung-Ho Chen, and Kuen-Jong Lee,
    Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores,
    IEEE Transactions on Very Large Scale Integration Systems,
    Vol. 19, No. 3, pp. 516-520, March 2011. (SCI, EI)

  4. Wei-Cheng Lin and Chung-Ho Chen,
    Frame Buffer Access Reduction for MPEG Video Decoder,
    IEEE Transactions on Circuits and Systems for Video Technology,
    Vol. 18, No. 10, pp. 1452-1456, October 2008. (SCI, EI)

  5. Chung-Ming Chen and Chung-Ho Chen,
    Configurable VLSI Architecture for Deblocking Filter in H.264/AVC,
    IEEE Transactions on Very Large Scale Integration Systems,
    Vol. 16, No. 8, pp. 1072-1082, August 2008. (SCI, EI)

  6. Chung-Ho Chen and Kuo-Su Hsiao,
    Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality,
    IEEE Transactions on Computers,
    Vol. 56, No. 11, pp. 1534-1548, November 2007. (SCI, EI)

  7. Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao,
    Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores,
    IEEE Transactions on Very Large Scale Integration Systems,
    Vol. 15, No. 5, pp. 505-517, May 2007. (SCI, EI)

  8. Kuo-Su Hsiao and Chung-Ho Chen,
    Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation,
    IEEE Transactions on Very Large Scale Integration Systems,
    Vol. 14, No. 10, pp. 1089-1102, October 2006. (SCI, EI)

  9. C. -H. Chen and F.-F Lin,
    An Easy-to-Use Approach for Practical Bus-Based System Design,
    IEEE Transactions on Computers,
    Vol. 48, No. 8, pp. 780-793, August 1999. 國科會甲種研究獎 (SCI, EI)

  10. C. -H. Chen and A. K. Somani,
    Fault-Containment in Cache Memories for TMR Redundant Processor Systems,
    IEEE Transactions on Computers,
    Vol. 48, No. 4, pp. 386-39, April 1999. 國科會甲種研究獎 (SCI, EI)

  11. C. -H. Chen and A. K. Somani,
    Architecture Technique Trade-Offs Using Mean Memory Delay Time,
    IEEE Transactions on Computers,
    Vol. 45, No. 10, pp. 1089-1100, October 1996. 國科會甲種研究獎 (SCI, EI)

  12. Craig M. Wittenbrink, A. K. Somani, and C. -H. Chen,
    Cache Write Generate for Parallel Image Processing on Shared Memory Architectures,
    IEEE Transactions on Image Processing,
    Vol. 5, No. 7, pp. 1204-1208, July 1996. (SCI, EI)

  13. C. -H. Chen and A. K. Somani,
    A Unified Architectural Tradeoff Methodology,
    ACM SIGARCH Computer Architecture News,
    Vol. 22, Iss. 2, pp. 348-357, April 1994.

其他期刊論文 (10)

  1. Chen-Chieh Wang, andChung-Ho Chen,
    A System‐Level Network Virtual Platform for IPsec Processor Development,
    IEICE Transactions on Information and Systems,
    Vol.E96-D, No.5, pp.1095-1104, May 2013. (SCI, EI)

  2. Chung-Ming Chen, andChung-Ho Chen,
    Window Architecture for Deblocking Filter in H.264/AVC,
    International Journal of Innovative Computing, Information and Control,
    Vol. 3, No. 6, pp. 1677-1695, December 2007. (SCI, EI)

  3. Chung-Ho Chen, Chao-Hsien Hsu, and Chen-Chieh Wang,
    Scalable IPv6 Lookup/Update Design for High-Throughput Routers,
    Journal of Internet Technology,
    Vol. 8, No. 3, pp. 261-269, July 2007. (EI)

  4. Chung-Ming Chen and Chung-Ho Chen,
    An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC,
    IEICE Transactions on Information and Systems,
    Vol. E90-D, No.1 pp.99-107, January 2007. (SCI, EI)

  5. M.-D. Shieh, M.-H. Sheu, C.-H. Chen , and H.-F. Lo
    A Systematic Approach for Parallel CRC Computations,
    Journal of Information Science and Engineering,
    Vol. 17, No. 3, pp. 445-461, May 2001. (SCI)

  6. C.-H. Chen and Akida Wu,
    Address Prediction Using a Bit-Matrix Indexing Scheme for Selective Update,
    Journal of Computers,
    Vol. 12 No.3, September 2000.

  7. C.-H. Chen and Akida Wu,
    Performance Evaluation of Load/Store Issue and Memory Access Policies,
    Journal of the Chinese Institute of Engineers,
    Vol.23, No. 6, pp. 697-709, 2000. (SCI, EI)

  8. C.-H. Chen,
    Exploring the Design Space of Cache Memories, Bus Width, and Burst Transfer Memory Systems,
    Journal of the Chinese Institute of Engineers,
    Vol.21, No. 3, pp.269-282, 1998. (SCI, EI)

  9. R. M. Haralick, A. K. Somani, C. Wittenbrink, R. Johnson, K. Cooper,L. G. Shapiro, I. T. Phillips, J. N. Hwang, W. Cheung, Y.H. Yao, C. H. Chen, L. Yang, B. Daugherty, B. Lorbeski, K. Loving, T. Miller, L. Parkins, et. al.
    Proteus: A Reconfigurable Computational Network for Computer Vision,
    Journal of Machine Vision and Applications,
    Vol. 8, No. 2, pp. 85-100, March 1995. (SCI, EI)

  10. P. D. Stigall and C. -H. Chen,
    A Performance Simulation of Local Area Networks Using CSMA/CD and Token Bus Protocols,
    Computers & Electrical Engineering,
    Vol. 16, No.3, 1990. (SCI, EI)


會議論文

國際會議論文 (50)

  1. Yun-Chi Huang, Kuan-Chieh Hsu, Wan-shan Hsieh, Chen-Chieh Wang, Chia-Han Lu and Chung-Ho Chen,
    Dynamic SIMD re-convergence with paired-path comparison,
    in the IEEE International Symposium on Circuits and Syatem(ISCAS),
    May 22-25, 2016, Montreal, Canada.

  2. Chun-Po Huang, Ya-Ting Shyu, Tsung-Yu Hsieh, Chieh-Wen Cheng, Wei-Chiun Liu, Hao-Ting Jian, Ying-Wei Wang, Bin-Da Liu, Soon-Jyh Chang, Lih-Yih Chiou and Chung-Ho Chen,
    The SoC design of a versatile biomedical signal processor for potentiostat,
    in the International Bioelectronics and Bioinformatics Conference (ISBB),
    Oct 14-17, 2015, Beijing, China.

  3. Chien-Hsuan Yen, Chung-Ho Chen and Kuan-Chung Chen,
    A memory-efficient NoC system for OpenCL many-core platform,
    in the IEEE International Symposium on Circuits and Syatem(ISCAS),
    May 24-27, 2015, Lisbon, Portugal.

  4. Kuan-Chung Chen and Chung-Ho Chen,
    An OpenCL runtime system for a heterogeneous many-core virtual platform,
    in the IEEE International Symposium on Circuits and Syatem(ISCAS),
    June 1-5, 2014, Melbourne VIC, Australia.

  5. Jhe-Yu Liou and Chung-Ho Chen,
    Re-visit Blocking Texture Cache Design for Modern GPU,
    in the 11th International SoC Design Conference (ISOCC),
    Nov. 3-6, 2014, Jeju, Korea.

  6. Tzu-Hsuan Hsu, Ching-Wen Lin and Chung-Ho Chen,
    Using Condition Flag Prediction to Improve the Performance of Out-of-Order Processors,
    in the IEEE International Symposium on Circuits and Syatem(ISCAS) ,
    May 19-23, 2013 , Beijing, China.

  7. Chien-Te Liu, Kuan-Chung Chen and Chung-Ho Chen,
    CASL Hypervisor and its Virtualization Platform,
    in the IEEE International Symposium on Circuits and Syatem(ISCAS) ,
    May 19-23, 2013 , Beijing, China.
  8. Hsu-Yao Huang, Chi-Yuan Huang, and Chung-Ho Chen,
    Tile-Based GPU Optimizations through ESL Full System Simulation,
    in the IEEE International Symposium on Circuits and Systems (ISCAS),
    May 20-23, 2012, Seoul, Korea.

  9. Chen-Chieh Wang, Sheng-Hsin Lo, Yao-Ning Liu, and Chung-Ho Chen,
    NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development,
    in the IEEE International Symposium on Circuits and Systems (ISCAS),
    May 20-23, 2012, Seoul, Korea.

  10. Chen-Chieh Wang and Chung-Ho Chen,
    An Optimized Cryptographic Processing Unit for IPsec Processors,
    in the 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC),
    June 19-22, 2011, Gyeongju, Korea.

  11. Kuan-Chung Chen and Chung-Ho Chen,
    A Synchronization Profiler for Hybrid Full System Simulation Platform,
    in the International SoC Design Conference (ISOCC-2010),
    Nov. 22-23, 2010, Incheon, Korea.

  12. Xie-Zeng Shen, Shin-Ying Lee, and Chung-Ho Chen,
    Full System Simulation with QEMU: an Approach to Multi-View 3D GPU Design,
    in the IEEE International Symposium on Circuits and Systems (ISCAS),
    May 30 - June 2, 2010, Paris, France.

  13. Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, and Kuen-Jong Lee,
    Full System Simulation and Verification Framework,
    in the Proceedings of the Fifth International Conference on Information Assurance and Security (IAS-2009),
    August 18-20, 2009, Xi'an, China.

  14. Chen-Chieh Wang, Ro-Pun Wong, Jing-Wun Lin, and Chung-Ho Chen,
    System-Level Development and Verification Framework for High-Performance System Accelerator,
    in the IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT),
    April 27-30, 2009, Hsinchu, Taiwan.

  15. Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen,
    A Software-Based Test Methodology for Direct-Mapped Data Cache,
    in the IEEE Seventeenth Asian Test Symposium (ATS), November 24-27, 2008, Sapporo, Japan.

  16. Wei-Cheng Lin and Chung-Ho Chen,
    Avoiding Unnecessary Frame Memory Access and Multi-Frame Motion Estimation Computation in H.264/AVC,
    in the IEEE International Symposium on Circuits and Systems (ISCAS), May 18-21, 2008, Seattle, Washington, USA.

  17. Tai-Hua Lu, Chung-Ho Chen, and Kuen-Jong Lee,
    A Hybrid Self-Testing methodology of Processor Cores,
    in the IEEE International Symposium on Circuits and Systems (ISCAS), May 18-21, 2008, Seattle, Washington, USA.

  18. Yi-Ying Tsai, Chia-Jung Hsu, and Chung-Ho Chen,
    Address Compression for Scalable Load/Store Queue Implementation,
    in the IEEE International Symposium on Circuits and Systems (ISCAS), May 18-21, 2008, Seattle, Washington, USA.

  19. Tai-Hua Lu, Chung-Ho Chen, and Kuen-Jong Lee,
    A Hybrid Software-Based Self-Testing methodology for Embedded Processor,
    in the ACM Symposium on Applied Computing (SAC), March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)

  20. Yi-Ying Tsai, Chia-Jung Hsu, and Chung-Ho Chen,
    Power-efficient and Scalable Load/Store Queue Design via Address Compression,
    in the ACM Symposium on Applied Computing (SAC), March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)

  21. Wei-Cheng Lin and Chung-Ho Chen,
    A Data-Reuse Scheme for Avoiding Unnecessary Frame Buffer Accesses and Display RAM Accesses in MPEG-4 ASP Video Decoder,
    in the IEEE International SoC Conference (SOCC), September 26-29, 2007, Hsinchu, Taiwan.

  22. Yi-Cheng Chung, Stanley Lee, and Chung-Ho Chen,
    A Packet Forwarding Method for the iSCSI Virtualization Switch,
    in the 4th International Workshop on Storage Network Architecture and Parallel I/Os (SNAPI), September 24, 2007, San Diego, California, USA.

  23. Wei-Cheng Lin and Chung-Ho Chen,
    Reduction of Frame Memory Accesses and Motion Estimation Computations in MPEG-4 Video Encoder,
    in the 16th International Conference on Computer Communications and Networks (ICCCN), August 13-16, 2007, Honolulu, Hawaii, USA.

  24. Chung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, and Han-Chiang Chen,
    Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator,
    in the 31st Annual IEEE Conference on Local Computer Networks (LCN), November 14-16, 2006, Tampa, Florida, USA.

  25. Kuo-Su Hsiao and Chung-Ho Chen,
    Scheduler Optimization by Exploring Wakeup Locality,
    in the International Conference of Computer Engineering & Systems (ICCES), November 5-7, 2006, Egypt.

  26. Chung-Ming Chen, Chung-Ho Chen, Jian-Ping Zeng, and Chao-Tang Yu,
    Windows Processing for Deblocking Filter in H.264/AVC,
    in the Proceeding of the 32nd Annual Conference of the IEEE Industrial Electronics (IECON), November 7-10, 2006, Paris, France.

  27. Kuo-Su Hsiao and Chung-Ho Chen,
    Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling,
    in the International Conference of Computer Design, October, 2006, USA. (EI)

  28. Wei-Cheng Lin and Chung-Ho Chen,
    Exploring Reusable Frame Buffer Data for MPEG-4 Video Decoding,
    in the IEEE International Symposium on Circuits and Systems (ISCAS), 2006, Island of Kos, Greece. (EI)

  29. Chung-Ming Chen, Jian-Ping Zeng, Chung-Ho Chen, Chao-Tang Yu, and Yu-Pin Chang,
    Window Architecture for Deblocking Filter in H.264/AVC,
    in the 6th IEEE International Symposium on Signal Processing and Information Technology, August 27-30, 2006, Vancouver, Canada. (EI)

  30. Kuo-Su Hsiao and Chung-Ho Chen,
    An Efficient Wakeup Design for Energy Reduction in High-Performance Superscalar Processors,
    in the ACM SIGMicro International Conference on Computing Frontiers (CF), 2005, Italy. (EI)

  31. Chung-Ming Chen and Chung-Ho Chen,
    A Memory Efficient Architecture for Deblocking Filter in H.264 Using Vertical Processing Order,
    in the IEEE International Conference on Intelligent Sensors, Sensor Networks, and Information Processing (ISSNIP), 2005, Australia.

  32. Chung-Ming Chen and Chung-Ho Chen,
    Parallel Processing for Deblocking Filter in H.264/AVC,
    in the International Conference on Communications, Internet and Information Technology (CIIT), 2005, Cambridge, USA. (EI)

  33. Chung-Ming Chen and Chung-Ho Chen,
    Alternative Processing Order with Efficient Architecture for Adaptive Deblocking Filter in H.264/AVC,
    in the International Conference on Communications, Internet, and Information Technology (CIIT), 2005, Cambridge, USA. (EI)

  34. Chung-Ming Chen and Chung-Ho Chen,
    An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding,
    in the International Conference on Computer Graphics and Imaging (CGIM), 2005, Honolulu, Hawaii, USA. (EI)

  35. Chung-Ming Chen and Chung-Ho Chen,
    An Efficient VLSI Architecture for Edge Filtering in H.264/AVC,
    in the International Conference on Circuits, Signals, and Systems, 2005, Marina del Rey, CA, USA.

  36. F.-M Huang and C.-H. Chen,
    Memory Access Scheduling and Bank Precharge Strategies,
    in the poster proceeding of 12 th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 2004, Netherlands.

  37. Wei-Cheng Lin and Chung-Ho Chen,
    An Energy-Delay Efficient Power Management Scheme for Embedded System in Multimedia Applications,
    in Proceedings of The IEEE Asia Pacific Conference on Circuit & System (APCCAS),2004, Taiwan. (EI)

  38. N.-Y. Ker, and C.-H. Chen,
    An Effective SDRAM Power Mode Management Scheme for Performance and Energy Sensitive Embedded Systems,
    in the Proceeding of Asia and South Pacific Design Automation Conference (ASP-DAC), 2003, Japan.

  39. M.-C. Chen, I.–J. Huang, and C.-H. Chen,
    Parameterized MAC Unit Implementation,
    in the Proceeding of Asia and South Pacific Design Automation Conference,
    2001, Japan.
  40. C.-H. Chen, M. -.H Sheu, M.-D. Shieh, T.-S, Li, and M.-T. Chen,
    Design and Implementation of a 10/100 Mbps Ethernet Switching Hub Controller,
    in the Proceeding of the IEEE Asia Pacific Conference on Communications,
    1998, Singapore.

  41. Ming-Hwa Sheu, Chung-Ho Chen, Ming-Der Shieh and Tzung-Shiue Li,
    A High Performance VLSI Architecture Design for 10M /100Mbps Ethernet Switching Fabric,
    in the Proceeding of International Conference on Consumer Electronics,
    1998, USA. (EI)

  42. C. -H. Chen and A. Wu,
    Microarchitecture Support for Improving the Performance of Load Target Prediction,
    in the Proceeding of 30 th Annual IEEE/ACM International Symposium on Microarchitecture,
    December 1-3, 1997, Research Triangle Park, NC, USA. (EI)

  43. C. -H. Chen and A. Wu,
    An Enhanced DLX-based Superscalar System Simulator,
    in the 3rd Annual Workshop on Computer Architecture Education,
    February, 1997, San Antonio, Texas, USA.

  44. C. -H. Chen and A. Wu,
    An Enhanced DLX-based Superscalar System Simulator,
    in the IEEE Computer Architecture Newsletter,
    pp.25-31, September, 1997.

  45. C. -H. Chen and A. K. Somani,
    A Unified Architectural Tradeoff Methodology,
    in the Proceeding of the 21st International Symposium on Computer Architecture,
    pp. 348-357, April 18-21, 1994, Chicago, USA. 國科會甲種研究獎 (EI)

  46. C. -H. Chen and A. K. Somani,
    A Cache Protocol for Error Detection and Recovery in Fault-Tolerant Computing Systems,
    in the 24 th International Symposium on Fault-Tolerant Computing,
    pp. 278-287, June 15-17, 1994, Austin Texas, USA. 國科會甲種研究獎 (EI)

  47. R. M. Haralick, Y-H, Yao, L. G. Shapiro, I. T. Phillips, A. K. Somani, J. N. Hwang, M. Harrington, C. Wittenbrink, C. -H. Chen, X. Liu, and S. Chen,
    Proteus: Control and Management System,
    in the Proceedings of Workshop on Computer Architectures for Machine Perception,
    pp. 101-108, December 15-17, 1993, New Orleans, USA.

  48. C. -H. Chen and A. K. Somani,
    Error Detection and Recovery in Fault-Tolerant Processor Systems Using Caches,
    in Proceeding of the ISMM International Conference on Parallel and Distributed Computing and Systems,
    pp. 388-393, 1992, Pittsburgh, PA, USA.

  49. C. -H. Chen and A. K. Somani,
    Fault-Tolerant Parallel Processing with Real-Time Error Detection and Recovery,
    in Proceeding of the 26th Asilomar Conference on Signals, Systems & Computers,
    pp. 994-998, 1992, USA.

  50. C. -H. Chen and A. K. Somani,
    Effects of Cache Traffics on Shared-Bus Multiprocessor Systems,
    in Proceedings of the International Conference on Parallel Processing,
    pp. I285-I288, 1992, USA. (EI)

  51. Haralick-R-M. Somani-A-K. Wittenbrink-C. Johnson-R. Cooper-K. Shapiro-L-G. Phillips-I-T. Hwang-J-N. Cheung-W. Yao-Y-H. Chen-C-H . Yang-L. Daugherty-B. Lorbeski-B. Loving-K. Miller-T. Parkins-L. Soos-S.
    Proteus: a reconfigurable computational network for computer vision,
    Published by: IEEE Comput. Soc. Press. In Proceedings. 11th IAPR International Conference on Pattern Recognition.
    pp. 43-54, The Hague, Netherlands, 1992. (Judged among the 6 best papers).

  52. Haralick-R-M. Somani-A-K. Wittenbrink-C. Johnson-R. Cooper-K. Shapiro-L-G. Phillips-I-T. Jenq-Neng-Hwang. Cheung-W. Yung-Hsi-Yao. Chung-Ho-Chen . Yang-L. Duagherty-B. Lorbeski-B. Loving-K. Miller-T. Parkins-L. Soos-S.
    Proteus: a reconfigurable computational network for computer vision,
    in Proceedings of the SPIE - The International Society for Optical Engineering, vol.1659. pp. 54-76. 1992. Conf. Title: Image Processing and Interchange: Implementation and Systems,
    San Jose, CA, USA. SPIE. IS\&T. 12-14 Feb. 1992. (EI)

  53. C. M. Wittenbrink, A. K. Somani, and C. -H. Chen,
    Cache Write Generate for High Performance Parallel Processing,
    Abstract presented in the 19 th International Symposium on Computer Architecture,
    1992, USA. (EI)

  54. A. K. Somani, C. Wittenbrink, R. M. Haralick, L. G. Shapiro, J. N. Hwang, C. -H. Chen, R. Johnson, and K. Cooper,
    Proteus System Architecture and Organization,
    in the Proceeding of the Fifth International Parallel Processing Symposium,
    pp. 287-294, 1991.


國內會議論文 (8)

  1. Yi-Ying Tsai, Ke-Jia Lee, and Chung-Ho Chen,
    Code Compression Architecture for Memory Bandwidth Optimization in Embedded Systems,
    in the Proceeding of the International Computer Symposium (ICS), 2006, Taiwan.

  2. Po-Kai Chan, Chung-Ho Chen, and Cheng-Yeh Yu,
    An iWARP-Based TCP/IP Offload Engine,
    in the Proceeding of the 17th VLSI Design/CAD Symposium, August 8-11, 2006.

  3. W.-Z. Lin, and C.-H. Chen,
    10/100/1000 Mbps Ethernet MAC with Clock Management for AMBA System,
    in the Proceeding of the 13th VLSI Design/CAD Symposium, 2002.

  4. 盧偉聖、陳中和、蔡宜穎、林宇峰,
    The Design of a Digital Control Technology for Lighting and Special Effects,
    in the Proceeding of Taiwan Power Electronic Conference, 2002.

  5. C.-H. Chen, M.-D. Shieh, and Jimmy Shou,
    VLSI Architecture of an Instruction-Based Crypto Coprocessor,
    in the Proceeding of the 11th VLSI Design/CAD Symposium, 2000.

  6. 伍麗樵 , 黃胤傅 , 陳中和 , 陳惠淳 , 陳世仁 , 陳肇男 , 方志強 ,
    Download On Demand 多媒體影片租借系統之實作 ,
    第 15 屆全國技術及職業教育研討會論文集,
    pp. 171-179, 2000.

  7. S.-H. Sheu, C.-H. Chen, and T.-S Li,
    The Shared Bus Architecture Design and Chip Implementation for a 10M /100Mbps Ethernet Switching Fabric,
    in the Proceeding of the 8th VLSI Design/CAD Symposium,
    1997.

  8. J.-S. Lin, C.-H. Chen , C.-Y. Lin, and S.-H. Liu,
    The Application of Fuzzy Hopfield Neural Network for Vector Quantization in Image Compression, in the Proceeding of the fifth National Conference on Fuzzy Theory and Application,
    pp.66-71, 1997.


著書

  1. 嵌入式系統設計 - 以 ARM 處理器基礎之 SOC 平台,
    黃悅民、陳敬、侯廷偉、陳中和、黃慶祥、林志敏編著。
    ISBN 986-7287-63-0 滄海書局, March 2006.
    獲評選為優良教科書,教育部顧問室通訊科技人才培育先導型計畫寬頻網際網路組,
    台顧字第 0950179468 號 。

  2. TCP/IP 通訊協定 ( 第三版 ),
    陳中和王振傑譯。
    The McGraw-Hill Companies Inc.,
    ISBN-13: 978-986-157-321-2, Nov. 2006.

  3. 計算機組織與設計 ( 第三版 ) ,
    (by D. A. Patterson and J. L. Hennessy),陳中和 譯。
    台灣東華書局,ISBN 957-483-325-9,July 2005.

  4. TCP/IP 協定 ( 第二版 ),
    陳中和、吳秀峰譯。
    The McGraw-Hill Companies Inc., ISBN 957-493-812-3, Nov. 2003.

  5. 微電腦結構,
    陳中和 編著,
    東大圖書公司 , ISBN 957-19-2684-1, 2002.

  6. 微電腦實習,
    陳中和 編著,
    東大圖書公司 , ISBN 957-19-2683-3, 2002.

  7. TCP/IP 協定,
    陳中和、吳秀峰譯。
    The McGraw-Hill Companies Inc., ISBN 957-493-435-7, Sept. 2001.


專利

  1. 具多協定處理單位之儲存架構及方法,
    中華民國專利 I247991 號, 2006.

  2. Multiprocessor system with write generate method for updating cache,
    United States patent, No. 5524212, June 1996.

  3. Storage structure and method utilizing mutiple protocol processor units,
    United States patent, No. 7460550, Dec. 2008.


舉辦

  1. 主辦2011 IEEE CASS Workshop on Circuit and System New Curriculum for Interdisciplinary Reform and evelopment
  2. 2010 年擔任教育部嵌入式系統設計競賽主持人
member/advisor.txt · 上一次變更: 2017/01/24 10:30 由 admin