109學年度第2學期邏輯系統

需要加簽的同學

請於星期五2/26上課前 （1:00 pm）

提早到上課教室找助教登記

由於加簽人數過多

會以現場抽籤方式決定7位可加簽者

（p.s.可加簽人數為10%,即7位） |

• Lecture 1 Outlines and Numbers
• Lecture 2 Boolean Algebra Basic
• Lecture 2-1 Boolean Algebra
• Lecture 3 Algebraic Simplification
• Lecture 4 Minterm and Maxterm
• Lecture 5 Karnaugh maps
• Lecture 6 Quine-McCluskey Method
• Lecture 7 Multi-Level Gate Networks
• Lecture 8 Combinational network design
• Lecture 9-B MUX-DMUX Tree
• Lecture 9 Mux Decoder ROM
• Lecture 10 Latch and Flip-flop
• Lecture 11 Registers and Counters
• Lecture 11-1 FPGAs Shannon
• Lecture 12 Analysis of Clocked sequential network
• Lecture 13 Derivation of State Graphs and Tables
• Lecture 14 Reduction of State Tables
• Lecture 15 Sequential circuit design
• Lecture 16 Circuits for Arithmetic Operations
• Lecture 17 State Machine Charts

• Lecture 2 Supplement, Verilog
• Adder Multiplier Circuit
• Adder Mutiplier Circuit CLA
• Supplement on verilog for ASM chart
• Supplement on verilog with com ckt examples
• Supplement on verilog with FF examples
• Supplement on verilog with sequential circuits examples, FSM
• Supplement on verilog with adder examples 3-28
• Supplement on verilog with adder examples
• Multiplication and Division basics