計算機架構與系統實驗室

Computer Architecture and System Laboratory

使用者工具

網站工具

mbstring extension must be loaded in order to run mPDF
member:advisor

差異處

這裏顯示兩個版本的差異處。

連向這個比對檢視

Both sides previous revision 前次修改
下次修改 		前次修改
member:advisor [2014/10/06 16:32]
elvis 		member:advisor [2021/03/10 01:49] (目前版本)
admin [特殊榮譽]
行 1: 行 1:
-<WRAP todo round> //**本條目後半段還有很多沒搬遷完成**// </WRAP> 
- 
 ====== 陳中和教授 ====== ====== 陳中和教授 ======
  
 <WRAP group> <WRAP group>
 <WRAP 200px column> <WRAP 200px column>
-{{wiki:pic_adervisor.jpg?200 }}+{{wiki:pic_advisor.jpg?200 }}
 </WRAP> </WRAP>
  
行 13: 行 11:
     * [[chchen@mail.ncku.edu.tw]]     * [[chchen@mail.ncku.edu.tw]]
     * [[thomas.waipu@gmail.com]]     * [[thomas.waipu@gmail.com]]
-  * [[http://office.ee.ncku.edu.tw/nckueechinese/professor/T207-chchen/1c.htm|成大教師資料]]+  * [[http://www.ee.ncku.edu.tw/subpage_div/teacher_new_2/index2.php?teacher_id=157|成大教師資料]]
 </WRAP> </WRAP>
 </WRAP> </WRAP>
行 20: 行 18:
  
 ===== 學歷 ===== ===== 學歷 =====
---------------- 
   * 華盛頓大學電機博士(1993) \\ Ph.D., University of Washington, Seattle, U.S.A.    * 華盛頓大學電機博士(1993) \\ Ph.D., University of Washington, Seattle, U.S.A. 
  
行 28: 行 25:
 \\  \\ 
 ===== 主要經歷 ===== ===== 主要經歷 =====
-------------------- 
  
   * 國際電機電子工程師學會中華民國第一分會常務理事 (Since 2012)   * 國際電機電子工程師學會中華民國第一分會常務理事 (Since 2012)
行 47: 行 43:
 \\ \\
 ===== 學門專長 ===== ===== 學門專長 =====
-------------------- 
  
   * 計算機架構 \\ Computer Architecture   * 計算機架構 \\ Computer Architecture
行 65: 行 60:
 \\ \\
 ===== 特殊榮譽 ===== ===== 特殊榮譽 =====
---------------------+  - 2020 年, 陳中和 教授榮獲 國立成功大學 109年度產學合作成果  <wrap danger>**特優教師 優良獎**</wrap> 。 \\ \\ 
 +  - 2020 年, 陳中和 教授榮獲 科技部 109年度  <wrap danger>**傑出技術移轉貢獻獎**</wrap> 。 \\ \\ 
 +  - 2018 年, 陳中和 教授榮獲 國立成功大學 「 107學年度電資學院 <wrap danger>**教學優良教師獎**</wrap> 」。 \\ \\ 
 +  - 2018 年, 陳中和 教授指導學生董仲宣、丁淯卿、蔡期開、潘星羽 參加2018新思科技ARC盃AIoT電子設計大賽，榮獲<wrap danger>**優等獎**</wrap> 。 \\ \\
   - 2013 年, **2013 IEEE Circuits and Systems Society Region 10 Chapter of the Year Award** \\ \\   - 2013 年, **2013 IEEE Circuits and Systems Society Region 10 Chapter of the Year Award** \\ \\
   - 2012 年, 陳中和 教授榮獲 國立成功大學 「 101學年度 <wrap danger>**教學優良教師獎**</wrap> 」。 \\ \\   - 2012 年, 陳中和 教授榮獲 國立成功大學 「 101學年度 <wrap danger>**教學優良教師獎**</wrap> 」。 \\ \\
行 78: 行 76:
  
 \\ \\
-===== Referred Paper ===== +===== 期刊論文 ===== 
--------------------------- +==== IEEE/ACM Transactions 期刊論文 (13) ==== 
-==== IEEE/ACM Transactions Paper (13) ==== +  - __Kuan-Chung Chen__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2018_jnl_01.pdf|Enabling SIMT Execution Model on Homogeneous Multi-Core System}}, \\ //ACM Transactions on Architecture and Code Optimization//, \\ Volume 15 Issue 1, April 2018 \\ Article No. 6. **(SCI, EI)**  \\ \\ 
-  - __En-Hao Chang__, __[[Member:jay|Chen-Chieh Wang]]__, __Chien-Te Liu__, __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_jnl_01.pdf|Virtualization Technology for TCP/IP Offload Engine}}, \\ //IEEE Transactions on Cloud Computing//, Vol. 2, No. 2, April-June 2014. **(SCI, EI)** \\ \\ +  - __En-Hao Chang__, __[[Member:jay|Chen-Chieh Wang]]__, __Chien-Te Liu__, __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_jnl_01.pdf|Virtualization Technology for TCP/IP Offload Engine}}, \\ //IEEE Transactions on Cloud Computing//, \\ Vol. 2, No. 2, April-June 2014. **(SCI, EI)** \\ \\ 
-  - __Yi-Ying Tsai__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2011_jnl_02.pdf|Energy-efficient Trace Reuse Cache for Embedded Processor}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 19, No. 9, pp. 1681-1694, September 2011. **(SCI, EI)**  \\ \\ +  - __Yi-Ying Tsai__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2011_jnl_02.pdf|Energy-efficient Trace Reuse Cache for Embedded Processor}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 19, No. 9, pp. 1681-1694, September 2011. **(SCI, EI)**  \\ \\ 
-  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2011_jnl_01.pdf|Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 19, No. 3, pp. 516-520, March 2011. **(SCI, EI)**  \\ \\ +  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2011_jnl_01.pdf|Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 19, No. 3, pp. 516-520, March 2011. **(SCI, EI)**  \\ \\ 
-  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_02.pdf|Frame Buffer Access Reduction for MPEG Video Decoder}}, \\ //IEEE Transactions on Circuits and Systems for Video Technology//, Vol. 18, No. 10, pp. 1452-1456, October 2008. **(SCI, EI)**  \\ \\ +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_02.pdf|Frame Buffer Access Reduction for MPEG Video Decoder}}, \\ //IEEE Transactions on Circuits and Systems for Video Technology//, \\ Vol. 18, No. 10, pp. 1452-1456, October 2008. **(SCI, EI)**  \\ \\ 
-  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_01.pdf|Configurable VLSI Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 16, No. 8, pp. 1072-1082, August 2008. **(SCI, EI)**   \\ \\ +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_01.pdf|Configurable VLSI Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 16, No. 8, pp. 1072-1082, August 2008. **(SCI, EI)**   \\ \\ 
-  - __[[Member:Advisor|Chung-Ho Chen]]__ and Kuo-Su Hsiao, \\ {{research:caslab_2007_jnl_04.pdf|Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality}}, \\ //IEEE Transactions on Computers//, Vol. 56, No. 11, pp. 1534-1548, November 2007. **(SCI, EI)**  \\ \\ +  - __[[Member:Advisor|Chung-Ho Chen]]__ and Kuo-Su Hsiao, \\ {{research:caslab_2007_jnl_04.pdf|Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality}}, \\ //IEEE Transactions on Computers//, \\ Vol. 56, No. 11, pp. 1534-1548, November 2007. **(SCI, EI)**  \\ \\ 
-  - __[[Member:Advisor|Chung-Ho Chen]]__, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao, \\ {{research:caslab_2007_jnl_02.pdf|Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 15, No. 5, pp. 505-517, May 2007. **(SCI, EI)**  \\ \\ +  - __[[Member:Advisor|Chung-Ho Chen]]__, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao, \\ {{research:caslab_2007_jnl_02.pdf|Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 15, No. 5, pp. 505-517, May 2007. **(SCI, EI)**  \\ \\ 
-  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_jnl_01.pdf|Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 14, No. 10, pp. 1089-1102, October 2006. **(SCI, EI)**  \\ \\ +  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_jnl_01.pdf|Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 14, No. 10, pp. 1089-1102, October 2006. **(SCI, EI)**  \\ \\ 
-  - __[[member:advisor|C. -H. Chen]]__ and F.-F Lin, \\ {{research:caslab_1999_jnl_02.pdf|An Easy-to-Use Approach for Practical Bus-Based System Design}}, \\ //IEEE Transactions on Computers//, Vol. 48, No. 8, pp. 780-793, August 1999. 國科會甲種研究獎 (SCI, EI) \\ \\ +  - __[[member:advisor|C. -H. Chen]]__ and F.-F Lin, \\ {{research:caslab_1999_jnl_02.pdf|An Easy-to-Use Approach for Practical Bus-Based System Design}}, \\ //IEEE Transactions on Computers//, \\ Vol. 48, No. 8, pp. 780-793, August 1999. 國科會甲種研究獎 (SCI, EI) \\ \\ 
-  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1999_jnl_01.pdf|Fault-Containment in Cache Memories for TMR Redundant Processor Systems}}, \\ //IEEE Transactions on Computers//, Vol. 48, No. 4, pp. 386-39, April 1999. 國科會甲種研究獎 (SCI, EI) \\ \\ +  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1999_jnl_01.pdf|Fault-Containment in Cache Memories for TMR Redundant Processor Systems}}, \\ //IEEE Transactions on Computers//, \\ Vol. 48, No. 4, pp. 386-39, April 1999. 國科會甲種研究獎 (SCI, EI) \\ \\ 
-  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1996_jnl_02.pdf|Architecture Technique Trade-Offs Using Mean Memory Delay Time}}, \\ //IEEE Transactions on Computers//, Vol. 45, No. 10, pp. 1089-1100, October 1996. 國科會甲種研究獎 (SCI, EI) \\ \\ +  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1996_jnl_02.pdf|Architecture Technique Trade-Offs Using Mean Memory Delay Time}}, \\ //IEEE Transactions on Computers//, \\ Vol. 45, No. 10, pp. 1089-1100, October 1996. 國科會甲種研究獎 (SCI, EI) \\ \\ 
-  - Craig M. Wittenbrink, A. K. Somani, and __[[member:advisor|C. -H. Chen]]__, \\ {{research:caslab_1996_jnl_01.pdf|Cache Write Generate for Parallel Image Processing on Shared Memory Architectures}}, \\ //IEEE Transactions on Image Processing//, Vol. 5, No. 7, pp. 1204-1208, July 1996. (SCI, EI) \\ \\ +  - Craig M. Wittenbrink, A. K. Somani, and __[[member:advisor|C. -H. Chen]]__, \\ {{research:caslab_1996_jnl_01.pdf|Cache Write Generate for Parallel Image Processing on Shared Memory Architectures}}, \\ //IEEE Transactions on Image Processing//, \\ Vol. 5, No. 7, pp. 1204-1208, July 1996. (SCI, EI) \\ \\ 
-  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1994_jnl_01.pdf|A Unified Architectural Tradeoff Methodology}}, \\ //ACM SIGARCH Computer Architecture News//, Vol. 22, Iss. 2, pp. 348-357, April 1994.+  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1994_jnl_01.pdf|A Unified Architectural Tradeoff Methodology}}, \\ //ACM SIGARCH Computer Architecture News//, \\ Vol. 22, Iss. 2, pp. 348-357, April 1994.
  
-==== Other Journal Paper (10) ====+==== 其他期刊論文 (10) ==== 
 +  - __[[Member:jay|Chen-Chieh Wang]]__, and__[[Member:Advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2013_jnl_01.pdf|A System‐Level Network Virtual Platform for IPsec Processor Development}}, \\ //IEICE Transactions on Information and Systems//, \\ Vol.E96-D, No.5, pp.1095-1104, May 2013. **(SCI, EI)** \\ \\ 
 +  - __ Chung-Ming Chen__, and__[[Member:Advisor|Chung-Ho Chen]]__, \\ Window Architecture for Deblocking Filter in H.264/AVC, \\ //International Journal of Innovative Computing, Information and Control//, \\ Vol. 3, No. 6, pp. 1677-1695, December 2007. **(SCI, EI)** \\ \\ 
 +  - __[[Member:Advisor|Chung-Ho Chen]]__, Chao-Hsien Hsu, and __[[Member:jay|Chen-Chieh Wang]]__, \\ {{:research:caslab_2007_jnl_03.pdf|Scalable IPv6 Lookup/Update Design for High-Throughput Routers}}, \\ //Journal of Internet Technology//, \\ Vol. 8, No. 3, pp. 261-269, July 2007. **(EI)** \\ \\ 
 +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2007_jnl_01.pdf|An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC}}, \\ IEICE Transactions on Information and Systems, \\ Vol. E90-D, No.1 pp.99-107, January 2007. **(SCI, EI)** \\ \\ 
 +  - M.-D. Shieh, M.-H. Sheu, __[[Member:Advisor|C.-H. Chen]]__ , and H.-F. Lo \\ {{:research:caslab_2001_jnl_01.pdf|A Systematic Approach for Parallel CRC Computations}}, \\ //Journal of Information Science and Engineering,// \\ Vol. 17, No. 3, pp. 445-461, May 2001. **(SCI)** \\ \\ 
 +  - __[[Member:Advisor|C.-H. Chen]]__ and Akida Wu, \\ Address Prediction Using a Bit-Matrix Indexing Scheme for Selective Update, \\ //Journal of Computers,// \\ Vol. 12 No.3, September 2000. \\ \\ 
 +  - __[[Member:Advisor|C.-H. Chen]]__ and Akida Wu, \\ Performance Evaluation of Load/Store Issue and Memory Access Policies, \\ //Journal of the Chinese Institute of Engineers,// \\ Vol.23, No. 6, pp. 697-709, 2000. **(SCI, EI)** \\ \\ 
 +  - __[[Member:Advisor|C.-H. Chen]]__, \\ Exploring the Design Space of Cache Memories, Bus Width, and Burst Transfer Memory Systems, \\ //Journal of the Chinese Institute of Engineers,// \\ Vol.21, No. 3, pp.269-282, 1998. **(SCI, EI)** \\ \\ 
 +  - R. M. Haralick, A. K. Somani, C. Wittenbrink, R. Johnson, K. Cooper,L. G. Shapiro, I. T. Phillips, J. N. Hwang, W. Cheung, Y.H. Yao, __[[Member:Advisor|C. H. Chen]]__, L. Yang, B. Daugherty, B. Lorbeski, K. Loving, T. Miller, L. Parkins, et. al. \\ {{:research:caslab_1995_jnl_01.pdf|Proteus: A Reconfigurable Computational Network for Computer Vision}}, \\ //Journal of Machine Vision and Applications,// \\ Vol. 8, No. 2, pp. 85-100, March 1995. **(SCI, EI)** \\ \\ 
 +  - P. D. Stigall and __[[Member:Advisor|C. -H. Chen]]__, \\ A Performance Simulation of Local Area Networks Using CSMA/CD and Token Bus Protocols, \\ //Computers & Electrical Engineering,// \\ Vol. 16, No.3, 1990. **(SCI, EI)**
  
 \\ \\
-===== International Conference Paper (49) ===== +===== 會議論文 ===== 
----- +==== 國際會議論文 (50) ==== 
 +  - Yun-Chi Huang, Kuan-Chieh Hsu, Wan-shan Hsieh, Chen-Chieh Wang, Chia-Han Lu and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2016_cnf_01.pdf|Dynamic SIMD re-convergence with paired-path comparison}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)//, \\ May 22-25, 2016, Montreal, Canada.  \\ \\ 
 +  - Chun-Po Huang, Ya-Ting Shyu, Tsung-Yu Hsieh, Chieh-Wen Cheng, Wei-Chiun Liu, Hao-Ting Jian, Ying-Wei Wang, Bin-Da Liu, Soon-Jyh Chang, Lih-Yih Chiou and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2015_cnf_03.pdf|The SoC design of a versatile biomedical signal processor for potentiostat}}, \\ //in the International Bioelectronics and Bioinformatics Conference (ISBB)//, \\ Oct 14-17, 2015, Beijing, China.  \\ \\ 
 +  - Chien-Hsuan Yen, __[[Member:Advisor|Chung-Ho Chen]]__ and Kuan-Chung Chen, \\ {{:research:caslab_2015_cnf_01.pdf|A memory-efficient NoC system for OpenCL many-core platform}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)//, \\ May 24-27, 2015, Lisbon, Portugal.  \\ \\ 
 +  - Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2014_cnf_03.pdf|An OpenCL runtime system for a heterogeneous many-core virtual platform}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)//, \\ June 1-5, 2014, Melbourne VIC, Australia.  \\ \\ 
 +  - __[[en:member:elvis|Jhe-Yu Liou]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_01.pdf|Re-visit Blocking Texture Cache Design for Modern GPU}}, \\ //in the 11th International SoC Design Conference (ISOCC)//, \\ Nov. 3-6, 2014, Jeju, Korea. \\ \\ 
 +  - Tzu-Hsuan Hsu, Ching-Wen Lin and __[[member:advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2013_cnf_02.pdf|Using Condition Flag Prediction to Improve the Performance of Out-of-Order Processors}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)// , \\ May 19-23, 2013 , Beijing, China. \\ \\ 
 +  - Chien-Te Liu, Kuan-Chung Chen and __[[member:advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2013_cnf_01.pdf|CASL Hypervisor and its Virtualization Platform}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)// , \\ May 19-23, 2013 , Beijing, China. 
 +  - Hsu-Yao Huang, Chi-Yuan Huang, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|Tile-Based GPU Optimizations through ESL Full System Simulation}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 20-23, 2012, Seoul, Korea.  \\ \\ 
 +  - __[[Member:jay|Chen-Chieh Wang]]__, Sheng-Hsin Lo, Yao-Ning Liu, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 20-23, 2012, Seoul, Korea.  \\ \\ 
 +  - __[[Member:jay|Chen-Chieh Wang]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ An Optimized Cryptographic Processing Unit for IPsec Processors, \\ //in the 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)//, \\ June 19-22, 2011, Gyeongju, Korea.  \\ \\ 
 +  - Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ A Synchronization Profiler for Hybrid Full System Simulation Platform, \\ //in the International SoC Design Conference (ISOCC-2010)//, \\ Nov. 22-23, 2010, Incheon, Korea.  \\ \\ 
 +  - Xie-Zeng Shen, Shin-Ying Lee, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2010_cnf_01.pdf|Full System Simulation with QEMU: an Approach to Multi-View 3D GPU Design}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 30 - June 2, 2010, Paris, France.  \\ \\ 
 +  - Jing-Wun Lin, __[[Member:jay|Chen-Chieh Wang]]__, Chin-Yao Chang, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2009_cnf_02.pdf|Full System Simulation and Verification Framework}}, \\ //in the Proceedings of the Fifth International Conference on Information Assurance and Security (IAS-2009)//, \\ August 18-20, 2009, Xi'an, China.  \\ \\ 
 +  - __[[Member:jay|Chen-Chieh Wang]]__, Ro-Pun Wong, Jing-Wun Lin, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2009_cnf_01.pdf|System-Level Development and Verification Framework for High-Performance System Accelerator}}, \\ //in the IEEE International Symposium on VLSI Design//, Automation & Test (VLSI-DAT), \\ April 27-30, 2009, Hsinchu, Taiwan.  \\ \\ 
 +  - Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_cnf_06.pdf|A Software-Based Test Methodology for Direct-Mapped Data Cache}}, \\ //in the IEEE Seventeenth Asian Test Symposium (ATS)//, November 24-27, 2008, Sapporo, Japan.  \\ \\ 
 +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_cnf_05.pdf|Avoiding Unnecessary Frame Memory Access and Multi-Frame Motion Estimation Computation in H.264/AVC}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, May 18-21, 2008, Seattle, Washington, USA. \\ \\ 
 +  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2008_cnf_04.pdf|A Hybrid Self-Testing methodology of Processor Cores}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, May 18-21, 2008, Seattle, Washington, USA.  \\ \\ 
 +  - Yi-Ying Tsai, Chia-Jung Hsu, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_cnf_03.pdf|Address Compression for Scalable Load/Store Queue Implementation}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, May 18-21, 2008, Seattle, Washington, USA.  \\ \\ 
 +  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2008_cnf_02.pdf|A Hybrid Software-Based Self-Testing methodology for Embedded Processor}}, \\ //in the ACM Symposium on Applied Computing (SAC)//, March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)  \\ \\ 
 +  - Yi-Ying Tsai, Chia-Jung Hsu, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_cnf_01.pdf|Power-efficient and Scalable Load/Store Queue Design via Address Compression}}, \\ //in the ACM Symposium on Applied Computing (SAC)//, March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)  \\ \\ 
 +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2007_cnf_03.pdf|A Data-Reuse Scheme for Avoiding Unnecessary Frame Buffer Accesses and Display RAM Accesses in MPEG-4 ASP Video Decoder}}, \\ //in the IEEE International SoC Conference (SOCC)//, September 26-29, 2007, Hsinchu, Taiwan.  \\ \\ 
 +  - Yi-Cheng Chung, Stanley Lee, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2007_cnf_02.pdf|A Packet Forwarding Method for the iSCSI Virtualization Switch}}, \\ //in the 4th International Workshop on Storage Network Architecture and Parallel I/Os (SNAPI)//, September 24, 2007, San Diego, California, USA.  \\ \\ 
 +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2007_cnf_01.pdf|Reduction of Frame Memory Accesses and Motion Estimation Computations in MPEG-4 Video Encoder}}, \\ //in the 16th International Conference on Computer Communications and Networks (ICCCN)//, August 13-16, 2007, Honolulu, Hawaii, USA.  \\ \\ 
 +  - __[[Member:Advisor|Chung-Ho Chen]]__, Yi-Cheng Chung, Chen-Hua Wang, and Han-Chiang Chen, \\ {{research:caslab_2006_cnf_01.pdf|Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator}}, \\ //in the 31st Annual IEEE Conference on Local Computer Networks (LCN)//, November 14-16, 2006, Tampa, Florida, USA.  \\ \\ 
 +  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_cnf_02.pdf|Scheduler Optimization by Exploring Wakeup Locality}}, \\ //in the International Conference of Computer Engineering & Systems (ICCES)//, November 5-7, 2006, Egypt.  \\ \\ 
 +  - Chung-Ming Chen, __[[Member:Advisor|Chung-Ho Chen]]__, Jian-Ping Zeng, and Chao-Tang Yu, \\ {{research:caslab_2006_cnf_03.pdf|Windows Processing for Deblocking Filter in H.264/AVC}}, \\ //in the Proceeding of the 32nd Annual Conference of the IEEE Industrial Electronics (IECON)//, November 7-10, 2006, Paris, France.  \\ \\ 
 +  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_cnf_04.pdf|Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling}}, \\ //in the International Conference of Computer Design//, October, 2006, USA. **(EI)**  \\ \\ 
 +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_cnf_05.pdf|Exploring Reusable Frame Buffer Data for MPEG-4 Video Decoding}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, 2006, Island of Kos, Greece. **(EI)**  \\ \\ 
 +  - Chung-Ming Chen, Jian-Ping Zeng, __[[Member:Advisor|Chung-Ho Chen]]__, Chao-Tang Yu, and Yu-Pin Chang, \\ {{research:caslab_2006_cnf_06.pdf|Window Architecture for Deblocking Filter in H.264/AVC}}, \\ //in the 6th IEEE International Symposium on Signal Processing and Information Technology//, August 27-30, 2006, Vancouver, Canada. **(EI)**  \\ \\ 
 +  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2005_cnf_01.pdf|An Efficient Wakeup Design for Energy Reduction in High-Performance Superscalar Processors}}, \\ //in the ACM SIGMicro International Conference on Computing Frontiers (CF)//, 2005, Italy. **(EI)**  \\ \\ 
 +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2005_cnf_02.pdf|A Memory Efficient Architecture for Deblocking Filter in H.264 Using Vertical Processing Order}}, \\ //in the IEEE International Conference on Intelligent Sensors, Sensor Networks, and Information Processing (ISSNIP)//, 2005, Australia.  \\ \\ 
 +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2005_cnf_03.pdf|Parallel Processing for Deblocking Filter in H.264/AVC}}, \\ //in the International Conference on Communications, Internet and Information Technology (CIIT)//, 2005, Cambridge, USA. **(EI)**  \\ \\ 
 +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2005_cnf_04.pdf|Alternative Processing Order with Efficient Architecture for Adaptive Deblocking Filter in H.264/AVC}}, \\ //in the International Conference on Communications, Internet, and Information Technology (CIIT)//, 2005, Cambridge, USA. (EI)  \\ \\ 
 +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2005_cnf_05.pdf|An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding}}, \\ //in the International Conference on Computer Graphics and Imaging (CGIM)//, 2005, Honolulu, Hawaii, USA. **(EI)**  \\ \\ 
 +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2005_cnf_06.pdf|An Efficient VLSI Architecture for Edge Filtering in H.264/AVC}}, \\ //in the International Conference on Circuits, Signals, and Systems//, 2005, Marina del Rey, CA, USA.  \\ \\ 
 +  - F.-M Huang and __[[Member:Advisor|C.-H. Chen]]__, \\ Memory Access Scheduling and Bank Precharge Strategies, \\ //in the poster proceeding of 12 th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems//, 2004, Netherlands.  \\ \\ 
 +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2004_cnf_02.pdf|An Energy-Delay Efficient Power Management Scheme for Embedded System in Multimedia Applications}}, \\ //in Proceedings of The IEEE Asia Pacific Conference on Circuit & System (APCCAS)//,2004, Taiwan. **(EI)**  \\ \\ 
 +  - N.-Y. Ker, and __[[Member:Advisor|C.-H. Chen]]__, \\ An Effective SDRAM Power Mode Management Scheme for Performance and Energy Sensitive Embedded Systems, \\ //in the Proceeding of Asia and South Pacific Design Automation Conference (ASP-DAC)//, 2003, Japan.  \\ \\ 
 +  - M.-C. Chen, I.–J. Huang, and __[[Member:Advisor|C.-H. Chen]]__, \\ Parameterized MAC Unit Implementation, \\ //in the Proceeding of Asia and South Pacific Design Automation Conference,// \\ 2001, Japan. 
 +  - __[[Member:Advisor|C.-H. Chen]]__, M. -.H Sheu, M.-D. Shieh, T.-S, Li, and M.-T. Chen, \\ Design and Implementation of a 10/100 Mbps Ethernet Switching Hub Controller, \\ //in the Proceeding of the IEEE Asia Pacific Conference on Communications,// \\ 1998, Singapore. \\ \\  
 +  - Ming-Hwa Sheu, __[[member:advisor|Chung-Ho Chen]]__, Ming-Der Shieh and Tzung-Shiue Li, \\ A High Performance VLSI Architecture Design for 10M /100Mbps Ethernet Switching Fabric, \\ //in the Proceeding of International Conference on Consumer Electronics,// \\ 1998, USA. **(EI)** \\ \\  
 +  - __[[Member:Advisor|C. -H. Chen]]__ and A. Wu, \\ Microarchitecture Support for Improving the Performance of Load Target Prediction, \\ //in the Proceeding of 30 th Annual IEEE/ACM International Symposium on Microarchitecture,// \\ December 1-3, 1997, Research Triangle Park, NC, USA. **(EI)** \\ \\  
 +  - __[[Member:Advisor|C. -H. Chen]]__ and A. Wu, \\ An Enhanced DLX-based Superscalar System Simulator, \\ //in the 3rd Annual Workshop on Computer Architecture Education,// \\ February, 1997, San Antonio, Texas, USA. \\ \\  
 +  - __[[Member:Advisor|C. -H. Chen]]__ and A. Wu, \\ An Enhanced DLX-based Superscalar System Simulator, \\ //in the IEEE Computer Architecture Newsletter,// \\ pp.25-31, September, 1997. \\ \\  
 +  - __[[Member:Advisor|C. -H. Chen]]__ and A. K. Somani, \\ A Unified Architectural Tradeoff Methodology, \\ //in the Proceeding of the 21st International Symposium on Computer Architecture,// \\ pp. 348-357, April 18-21, 1994, Chicago, USA. 國科會甲種研究獎 **(EI)** \\ \\  
 +  - __[[Member:Advisor|C. -H. Chen]]__ and A. K. Somani, \\ A Cache Protocol for Error Detection and Recovery in Fault-Tolerant Computing Systems, \\ //in the 24 th International Symposium on Fault-Tolerant Computing//, \\ pp. 278-287, June 15-17, 1994, Austin Texas, USA. 國科會甲種研究獎 **(EI)** \\ \\  
 +  - R. M. Haralick, Y-H, Yao, L. G. Shapiro, I. T. Phillips, A. K. Somani, J. N. Hwang, M. Harrington, C. Wittenbrink, __[[Member:Advisor|C. -H. Chen]]__, X. Liu, and S. Chen, \\ Proteus: Control and Management System, \\ //in the Proceedings of Workshop on Computer Architectures for Machine Perception,// \\ pp. 101-108, December 15-17, 1993, New Orleans, USA. \\ \\  
 +  - __[[Member:Advisor|C. -H. Chen]]__ and A. K. Somani, \\ Error Detection and Recovery in Fault-Tolerant Processor Systems Using Caches, \\ //in Proceeding of the ISMM International Conference on Parallel and Distributed Computing and Systems,// \\ pp. 388-393, 1992, Pittsburgh, PA, USA. \\ \\  
 +  - __[[Member:Advisor|C. -H. Chen]]__ and A. K. Somani, \\ Fault-Tolerant Parallel Processing with Real-Time Error Detection and Recovery, \\ //in Proceeding of the 26th Asilomar Conference on Signals, Systems & Computers,// \\ pp. 994-998, 1992, USA. \\ \\  
 +  - __[[Member:Advisor|C. -H. Chen]]__ and A. K. Somani, \\ Effects of Cache Traffics on Shared-Bus Multiprocessor Systems, \\ //in Proceedings of the International Conference on Parallel Processing,// \\ pp. I285-I288, 1992, USA. **(EI)** \\ \\  
 +  - Haralick-R-M. Somani-A-K. Wittenbrink-C. Johnson-R. Cooper-K. Shapiro-L-G. Phillips-I-T. Hwang-J-N. Cheung-W. Yao-Y-H. __[[member:advisor|Chen-C-H]]__ . Yang-L. Daugherty-B. Lorbeski-B. Loving-K. Miller-T. Parkins-L. Soos-S. \\ Proteus: a reconfigurable computational network for computer vision, \\ //Published by: IEEE Comput. Soc. Press. In Proceedings. 11th IAPR International Conference on Pattern Recognition.// \\ pp. 43-54, The Hague, Netherlands, 1992. (Judged among the 6 best papers). \\ \\  
 +  - Haralick-R-M. Somani-A-K. Wittenbrink-C. Johnson-R. Cooper-K. Shapiro-L-G. Phillips-I-T. Jenq-Neng-Hwang. Cheung-W. Yung-Hsi-Yao. __[[member:advisor|Chung-Ho-Chen]]__ . Yang-L. Duagherty-B. Lorbeski-B. Loving-K. Miller-T. Parkins-L. Soos-S. \\ Proteus: a reconfigurable computational network for computer vision, \\ //in Proceedings of the SPIE - The International Society for Optical Engineering, vol.1659. pp. 54-76. 1992. Conf. Title: Image Processing and Interchange: Implementation and Systems,// \\  San Jose, CA, USA. SPIE. IS\&T. 12-14 Feb. 1992. **(EI)** \\ \\  
 +  - C. M. Wittenbrink, A. K. Somani, and __[[Member:Advisor|C. -H. Chen]]__, \\ Cache Write Generate for High Performance Parallel Processing, \\ //Abstract presented in the 19 th International Symposium on Computer Architecture,// \\ 1992, USA. (EI) \\ \\  
 +  - A. K. Somani, C. Wittenbrink, R. M. Haralick, L. G. Shapiro, J. N. Hwang, __[[Member:Advisor|C. -H. Chen]]__, R. Johnson, and K. Cooper, \\ Proteus System Architecture and Organization, \\ //in the Proceeding of the Fifth International Parallel Processing Symposium,// \\ pp. 287-294, 1991.
 \\ \\
-===== Local Conference Paper (8) ===== +==== 國內會議論文 (8) ==== 
----- +  - Yi-Ying Tsai, Ke-Jia Lee, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_cnf_07.pdf|Code Compression Architecture for Memory Bandwidth Optimization in Embedded Systems}}, \\ //in the Proceeding of the International Computer Symposium (ICS)//, 2006, Taiwan.  \\ \\ 
 +  - Po-Kai Chan, __[[Member:Advisor|Chung-Ho Chen]]__, and Cheng-Yeh Yu, \\ An iWARP-Based TCP/IP Offload Engine, \\ //in the Proceeding of the 17th VLSI Design/CAD Symposium//, August 8-11, 2006.  \\ \\ 
 +  - W.-Z. Lin, and __[[Member:Advisor|C.-H. Chen]]__, \\ 10/100/1000 Mbps Ethernet MAC with Clock Management for AMBA System, \\ //in the Proceeding of the 13th VLSI Design/CAD Symposium//, 2002.  \\ \\ 
 +  - 盧偉聖、__[[Member:Advisor|陳中和]]__、蔡宜穎、林宇峰, \\ The Design of a Digital Control Technology for Lighting and Special Effects, \\ //in the Proceeding of Taiwan Power Electronic Conference//, 2002.  \\ \\ 
 +  - __[[Member:Advisor|C.-H. Chen]]__, M.-D. Shieh, and Jimmy Shou, \\ VLSI Architecture of an Instruction-Based Crypto Coprocessor, \\ //in the Proceeding of the 11th VLSI Design/CAD Symposium//, 2000.  \\ \\ 
 +  - 伍麗樵 , 黃胤傅 , __[[member:advisor|陳中和]]__ , 陳惠淳 , 陳世仁 , 陳肇男 , 方志強 , \\ Download On Demand 多媒體影片租借系統之實作 , \\ //第 15 屆全國技術及職業教育研討會論文集//, \\ pp. 171-179, 2000.  \\ \\ 
 +  - S.-H. Sheu, //[[member:advisor|C.-H. Chen]]//, and T.-S Li, \\ The Shared Bus Architecture Design and Chip Implementation for a 10M /100Mbps Ethernet Switching Fabric, \\ //in the Proceeding of the 8th VLSI Design/CAD Symposium,// \\ 1997.  \\ \\ 
 +  - J.-S. Lin, __[[member:advisor|C.-H. Chen]]__ , C.-Y. Lin, and S.-H. Liu, \\ The Application of Fuzzy Hopfield Neural Network for Vector Quantization in Image Compression, //in the Proceeding of the fifth National Conference on Fuzzy Theory and Application,// \\ pp.66-71, 1997. 
 +\\ 
 +===== 著書 ===== 
 +  - 嵌入式系統設計 - 以 ARM 處理器基礎之 SOC 平台， \\ 黃悅民、[[http://office.ee.ncku.edu.tw/nckueechinese/professor/T210-jchen/T0000000c.htm|陳敬]]、侯廷偉、__[[member:advisor|陳中和]]__、黃慶祥、林志敏編著。 \\ ISBN 986-7287-63-0 滄海書局， March 2006. \\ 獲評選為優良教科書，教育部顧問室通訊科技人才培育先導型計畫寬頻網際網路組， \\ 台顧字第 0950179468 號 。 \\ \\ 
 +  - TCP/IP 通訊協定 ( 第三版 )， \\ __[[member:advisor|陳中和]]__、__[[member:jay|王振傑]]__譯。 \\ The McGraw-Hill Companies Inc., \\ ISBN-13: 978-986-157-321-2, Nov. 2006. \\ \\ 
 +  - 計算機組織與設計 ( 第三版 ) ， \\ (by D. A. Patterson and J. L. Hennessy)，__[[member:advisor|陳中和]]__ 譯。 \\ 台灣東華書局，ISBN 957-483-325-9，July 2005. \\ \\ 
 +  - TCP/IP 協定 ( 第二版 )， \\ __[[member:advisor|陳中和]]__、吳秀峰譯。 \\ The McGraw-Hill Companies Inc., ISBN 957-493-812-3, Nov. 2003. \\ \\ 
 +  - 微電腦結構， \\ __[[member:advisor|陳中和]]__ 編著， \\ 東大圖書公司 , ISBN 957-19-2684-1, 2002. \\ \\ 
 +  - 微電腦實習， \\ __[[member:advisor|陳中和]]__ 編著， \\ 東大圖書公司 , ISBN 957-19-2683-3, 2002. \\ \\ 
 +  - TCP/IP 協定， \\ __[[member:advisor|陳中和]]__、吳秀峰譯。 \\ The McGraw-Hill Companies Inc., ISBN 957-493-435-7, Sept. 2001.
 \\ \\
-===== 著書 Books ===== +===== 專利 ===== 
-----+  - 具多協定處理單位之儲存架構及方法, \\ 中華民國專利 I247991 號, 2006. \\ \\ 
 +  - Multiprocessor system with write generate method for updating cache, \\ United States patent, No. 5524212, June 1996. \\ \\ 
 +  - Storage structure and method utilizing mutiple protocol processor units, \\ United States patent, No. 7460550, Dec. 2008.
  
 \\ \\
-===== 專利 Patents ===== +===== 舉辦 ===== 
-----+  - 主辦2011 IEEE CASS Workshop on Circuit and System New Curriculum for Interdisciplinary Reform and evelopment 
 +  - 2010 年擔任教育部嵌入式系統設計競賽主持人
member/advisor.1412613150.txt.gz · 上一次變更: 2014/11/10 02:36 (外部編輯)

頁面工具

若無特別註明，本 wiki 上的內容都是採用以下授權方式： CC Attribution-Share Alike 4.0 International
CC Attribution-Share Alike 4.0 International Donate Powered by PHP Valid HTML5 Valid CSS Driven by DokuWiki