計算機架構與系統實驗室

Computer Architecture and System Laboratory

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en:member:advisor [2014/11/14 15:37]
elvis [Prof. Chung-Ho Chen] 		en:member:advisor [2014/11/22 15:38] (current)
elvis
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 ===== Education ===== ===== Education =====
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   * Ph.D.(1993), University of Washington, Seattle, U.S.A.    * Ph.D.(1993), University of Washington, Seattle, U.S.A. 
  
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 \\  \\ 
 ===== Main Experience ===== ===== Main Experience =====
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   * 國際電機電子工程師學會中華民國第一分會常務理事 (Since 2012)   * 國際電機電子工程師學會中華民國第一分會常務理事 (Since 2012)
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 ===== Specialties ===== ===== Specialties =====
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   * Computer Architecture   * Computer Architecture
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 ===== Honor ===== ===== Honor =====
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   - 2013 年, **2013 IEEE Circuits and Systems Society Region 10 Chapter of the Year Award** \\ \\   - 2013 年, **2013 IEEE Circuits and Systems Society Region 10 Chapter of the Year Award** \\ \\
   - 2012 年, 陳中和 教授榮獲 國立成功大學 「 101學年度 <wrap danger>**教學優良教師獎**</wrap> 」。 \\ \\   - 2012 年, 陳中和 教授榮獲 國立成功大學 「 101學年度 <wrap danger>**教學優良教師獎**</wrap> 」。 \\ \\
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 ===== Referred Paper ===== ===== Referred Paper =====
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 ==== IEEE/ACM Transactions Paper (13) ==== ==== IEEE/ACM Transactions Paper (13) ====
-  - __En-Hao Chang__, __[[Member:jay|Chen-Chieh Wang]]__, __Chien-Te Liu__, __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_jnl_01.pdf|Virtualization Technology for TCP/IP Offload Engine}}, \\ //IEEE Transactions on Cloud Computing//, Vol. 2, No. 2, April-June 2014. **(SCI, EI)** \\ \\ +  - __En-Hao Chang__, __[[Member:jay|Chen-Chieh Wang]]__, __Chien-Te Liu__, __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_jnl_01.pdf|Virtualization Technology for TCP/IP Offload Engine}}, \\ //IEEE Transactions on Cloud Computing//, \\ Vol. 2, No. 2, April-June 2014. **(SCI, EI)** \\ \\ 
-  - __Yi-Ying Tsai__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2011_jnl_02.pdf|Energy-efficient Trace Reuse Cache for Embedded Processor}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 19, No. 9, pp. 1681-1694, September 2011. **(SCI, EI)**  \\ \\ +  - __Yi-Ying Tsai__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2011_jnl_02.pdf|Energy-efficient Trace Reuse Cache for Embedded Processor}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 19, No. 9, pp. 1681-1694, September 2011. **(SCI, EI)**  \\ \\ 
-  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2011_jnl_01.pdf|Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 19, No. 3, pp. 516-520, March 2011. **(SCI, EI)**  \\ \\ +  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2011_jnl_01.pdf|Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 19, No. 3, pp. 516-520, March 2011. **(SCI, EI)**  \\ \\ 
-  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_02.pdf|Frame Buffer Access Reduction for MPEG Video Decoder}}, \\ //IEEE Transactions on Circuits and Systems for Video Technology//, Vol. 18, No. 10, pp. 1452-1456, October 2008. **(SCI, EI)**  \\ \\ +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_02.pdf|Frame Buffer Access Reduction for MPEG Video Decoder}}, \\ //IEEE Transactions on Circuits and Systems for Video Technology//, \\ Vol. 18, No. 10, pp. 1452-1456, October 2008. **(SCI, EI)**  \\ \\ 
-  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_01.pdf|Configurable VLSI Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 16, No. 8, pp. 1072-1082, August 2008. **(SCI, EI)**   \\ \\ +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_01.pdf|Configurable VLSI Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 16, No. 8, pp. 1072-1082, August 2008. **(SCI, EI)**   \\ \\ 
-  - __[[Member:Advisor|Chung-Ho Chen]]__ and Kuo-Su Hsiao, \\ {{research:caslab_2007_jnl_04.pdf|Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality}}, \\ //IEEE Transactions on Computers//, Vol. 56, No. 11, pp. 1534-1548, November 2007. **(SCI, EI)**  \\ \\ +  - __[[Member:Advisor|Chung-Ho Chen]]__ and Kuo-Su Hsiao, \\ {{research:caslab_2007_jnl_04.pdf|Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality}}, \\ //IEEE Transactions on Computers//, \\ Vol. 56, No. 11, pp. 1534-1548, November 2007. **(SCI, EI)**  \\ \\ 
-  - __[[Member:Advisor|Chung-Ho Chen]]__, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao, \\ {{research:caslab_2007_jnl_02.pdf|Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 15, No. 5, pp. 505-517, May 2007. **(SCI, EI)**  \\ \\ +  - __[[Member:Advisor|Chung-Ho Chen]]__, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao, \\ {{research:caslab_2007_jnl_02.pdf|Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 15, No. 5, pp. 505-517, May 2007. **(SCI, EI)**  \\ \\ 
-  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_jnl_01.pdf|Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 14, No. 10, pp. 1089-1102, October 2006. **(SCI, EI)**  \\ \\ +  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_jnl_01.pdf|Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 14, No. 10, pp. 1089-1102, October 2006. **(SCI, EI)**  \\ \\ 
-  - __[[member:advisor|C. -H. Chen]]__ and F.-F Lin, \\ {{research:caslab_1999_jnl_02.pdf|An Easy-to-Use Approach for Practical Bus-Based System Design}}, \\ //IEEE Transactions on Computers//, Vol. 48, No. 8, pp. 780-793, August 1999. 國科會甲種研究獎 (SCI, EI) \\ \\ +  - __[[member:advisor|C. -H. Chen]]__ and F.-F Lin, \\ {{research:caslab_1999_jnl_02.pdf|An Easy-to-Use Approach for Practical Bus-Based System Design}}, \\ //IEEE Transactions on Computers//, \\ Vol. 48, No. 8, pp. 780-793, August 1999. 國科會甲種研究獎 (SCI, EI) \\ \\ 
-  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1999_jnl_01.pdf|Fault-Containment in Cache Memories for TMR Redundant Processor Systems}}, \\ //IEEE Transactions on Computers//, Vol. 48, No. 4, pp. 386-39, April 1999. 國科會甲種研究獎 (SCI, EI) \\ \\ +  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1999_jnl_01.pdf|Fault-Containment in Cache Memories for TMR Redundant Processor Systems}}, \\ //IEEE Transactions on Computers//, \\ Vol. 48, No. 4, pp. 386-39, April 1999. 國科會甲種研究獎 (SCI, EI) \\ \\ 
-  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1996_jnl_02.pdf|Architecture Technique Trade-Offs Using Mean Memory Delay Time}}, \\ //IEEE Transactions on Computers//, Vol. 45, No. 10, pp. 1089-1100, October 1996. 國科會甲種研究獎 (SCI, EI) \\ \\ +  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1996_jnl_02.pdf|Architecture Technique Trade-Offs Using Mean Memory Delay Time}}, \\ //IEEE Transactions on Computers//, \\ Vol. 45, No. 10, pp. 1089-1100, October 1996. 國科會甲種研究獎 (SCI, EI) \\ \\ 
-  - Craig M. Wittenbrink, A. K. Somani, and __[[member:advisor|C. -H. Chen]]__, \\ {{research:caslab_1996_jnl_01.pdf|Cache Write Generate for Parallel Image Processing on Shared Memory Architectures}}, \\ //IEEE Transactions on Image Processing//, Vol. 5, No. 7, pp. 1204-1208, July 1996. (SCI, EI) \\ \\ +  - Craig M. Wittenbrink, A. K. Somani, and __[[member:advisor|C. -H. Chen]]__, \\ {{research:caslab_1996_jnl_01.pdf|Cache Write Generate for Parallel Image Processing on Shared Memory Architectures}}, \\ //IEEE Transactions on Image Processing//, \\ Vol. 5, No. 7, pp. 1204-1208, July 1996. (SCI, EI) \\ \\ 
-  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1994_jnl_01.pdf|A Unified Architectural Tradeoff Methodology}}, \\ //ACM SIGARCH Computer Architecture News//, Vol. 22, Iss. 2, pp. 348-357, April 1994.+  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1994_jnl_01.pdf|A Unified Architectural Tradeoff Methodology}}, \\ //ACM SIGARCH Computer Architecture News//, \\ Vol. 22, Iss. 2, pp. 348-357, April 1994. 
  
 ==== Other Journal Paper (10) ==== ==== Other Journal Paper (10) ====
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 ===== Conference Paper ===== ===== Conference Paper =====
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 ==== International Conference Paper (50) ==== ==== International Conference Paper (50) ====
   - __[[en:member:elvis|Jhe-Yu Liou]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_01.pdf|Re-visit Blocking Texture Cache Design for Modern GPU}}, \\ //in the 11th International SoC Design Conference (ISOCC)//, \\ Nov. 3-6, 2014, Jeju, Korea. \\ \\   - __[[en:member:elvis|Jhe-Yu Liou]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_01.pdf|Re-visit Blocking Texture Cache Design for Modern GPU}}, \\ //in the 11th International SoC Design Conference (ISOCC)//, \\ Nov. 3-6, 2014, Jeju, Korea. \\ \\
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 ===== Patents ===== ===== Patents =====
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   - 具多協定處理單位之儲存架構及方法, \\ R.O.C(Taiwan) patent, No. I247991, 2006. \\ \\   - 具多協定處理單位之儲存架構及方法, \\ R.O.C(Taiwan) patent, No. I247991, 2006. \\ \\
   - Multiprocessor system with write generate method for updating cache, \\ United States patent, No. 5524212, June 1996. \\ \\   - Multiprocessor system with write generate method for updating cache, \\ United States patent, No. 5524212, June 1996. \\ \\
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 ===== Holding ===== ===== Holding =====
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   - 主辦2011 IEEE CASS Workshop on Circuit and System New Curriculum for Interdisciplinary Reform and evelopment   - 主辦2011 IEEE CASS Workshop on Circuit and System New Curriculum for Interdisciplinary Reform and evelopment
   - 2010 年擔任教育部嵌入式系統設計競賽主持人   - 2010 年擔任教育部嵌入式系統設計競賽主持人
en/member/advisor.1415979431.txt.gz · Last modified: 2014/11/14 15:37 by elvis

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