計算機架構與系統實驗室

Computer Architecture and System Laboratory

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member:advisor [2014/11/14 15:25]
elvis [著書] 		member:advisor [2021/03/10 01:49] (目前版本)
admin [特殊榮譽]
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     * [[chchen@mail.ncku.edu.tw]]     * [[chchen@mail.ncku.edu.tw]]
     * [[thomas.waipu@gmail.com]]     * [[thomas.waipu@gmail.com]]
-  * [[http://office.ee.ncku.edu.tw/nckueechinese/professor/T207-chchen/1c.htm|成大教師資料]]+  * [[http://www.ee.ncku.edu.tw/subpage_div/teacher_new_2/index2.php?teacher_id=157|成大教師資料]]
 </WRAP> </WRAP>
 </WRAP> </WRAP>
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 ===== 學歷 ===== ===== 學歷 =====
---------------- 
   * 華盛頓大學電機博士(1993) \\ Ph.D., University of Washington, Seattle, U.S.A.    * 華盛頓大學電機博士(1993) \\ Ph.D., University of Washington, Seattle, U.S.A. 
  
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 \\  \\ 
 ===== 主要經歷 ===== ===== 主要經歷 =====
-------------------- 
  
   * 國際電機電子工程師學會中華民國第一分會常務理事 (Since 2012)   * 國際電機電子工程師學會中華民國第一分會常務理事 (Since 2012)
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 \\ \\
 ===== 學門專長 ===== ===== 學門專長 =====
-------------------- 
  
   * 計算機架構 \\ Computer Architecture   * 計算機架構 \\ Computer Architecture
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 \\ \\
 ===== 特殊榮譽 ===== ===== 特殊榮譽 =====
---------------------+  - 2020 年, 陳中和 教授榮獲 國立成功大學 109年度產學合作成果  <wrap danger>**特優教師 優良獎**</wrap> 。 \\ \\ 
 +  - 2020 年, 陳中和 教授榮獲 科技部 109年度  <wrap danger>**傑出技術移轉貢獻獎**</wrap> 。 \\ \\ 
 +  - 2018 年, 陳中和 教授榮獲 國立成功大學 「 107學年度電資學院 <wrap danger>**教學優良教師獎**</wrap> 」。 \\ \\ 
 +  - 2018 年, 陳中和 教授指導學生董仲宣、丁淯卿、蔡期開、潘星羽 參加2018新思科技ARC盃AIoT電子設計大賽，榮獲<wrap danger>**優等獎**</wrap> 。 \\ \\
   - 2013 年, **2013 IEEE Circuits and Systems Society Region 10 Chapter of the Year Award** \\ \\   - 2013 年, **2013 IEEE Circuits and Systems Society Region 10 Chapter of the Year Award** \\ \\
   - 2012 年, 陳中和 教授榮獲 國立成功大學 「 101學年度 <wrap danger>**教學優良教師獎**</wrap> 」。 \\ \\   - 2012 年, 陳中和 教授榮獲 國立成功大學 「 101學年度 <wrap danger>**教學優良教師獎**</wrap> 」。 \\ \\
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 \\ \\
-===== Referred Paper ===== +===== 期刊論文 ===== 
--------------------------- +==== IEEE/ACM Transactions 期刊論文 (13) ==== 
-==== IEEE/ACM Transactions Paper (13) ==== +  - __Kuan-Chung Chen__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2018_jnl_01.pdf|Enabling SIMT Execution Model on Homogeneous Multi-Core System}}, \\ //ACM Transactions on Architecture and Code Optimization//, \\ Volume 15 Issue 1, April 2018 \\ Article No. 6. **(SCI, EI)**  \\ \\ 
-  - __En-Hao Chang__, __[[Member:jay|Chen-Chieh Wang]]__, __Chien-Te Liu__, __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_jnl_01.pdf|Virtualization Technology for TCP/IP Offload Engine}}, \\ //IEEE Transactions on Cloud Computing//, Vol. 2, No. 2, April-June 2014. **(SCI, EI)** \\ \\ +  - __En-Hao Chang__, __[[Member:jay|Chen-Chieh Wang]]__, __Chien-Te Liu__, __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_jnl_01.pdf|Virtualization Technology for TCP/IP Offload Engine}}, \\ //IEEE Transactions on Cloud Computing//, \\ Vol. 2, No. 2, April-June 2014. **(SCI, EI)** \\ \\ 
-  - __Yi-Ying Tsai__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2011_jnl_02.pdf|Energy-efficient Trace Reuse Cache for Embedded Processor}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 19, No. 9, pp. 1681-1694, September 2011. **(SCI, EI)**  \\ \\ +  - __Yi-Ying Tsai__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2011_jnl_02.pdf|Energy-efficient Trace Reuse Cache for Embedded Processor}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 19, No. 9, pp. 1681-1694, September 2011. **(SCI, EI)**  \\ \\ 
-  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2011_jnl_01.pdf|Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 19, No. 3, pp. 516-520, March 2011. **(SCI, EI)**  \\ \\ +  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2011_jnl_01.pdf|Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 19, No. 3, pp. 516-520, March 2011. **(SCI, EI)**  \\ \\ 
-  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_02.pdf|Frame Buffer Access Reduction for MPEG Video Decoder}}, \\ //IEEE Transactions on Circuits and Systems for Video Technology//, Vol. 18, No. 10, pp. 1452-1456, October 2008. **(SCI, EI)**  \\ \\ +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_02.pdf|Frame Buffer Access Reduction for MPEG Video Decoder}}, \\ //IEEE Transactions on Circuits and Systems for Video Technology//, \\ Vol. 18, No. 10, pp. 1452-1456, October 2008. **(SCI, EI)**  \\ \\ 
-  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_01.pdf|Configurable VLSI Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 16, No. 8, pp. 1072-1082, August 2008. **(SCI, EI)**   \\ \\ +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_01.pdf|Configurable VLSI Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 16, No. 8, pp. 1072-1082, August 2008. **(SCI, EI)**   \\ \\ 
-  - __[[Member:Advisor|Chung-Ho Chen]]__ and Kuo-Su Hsiao, \\ {{research:caslab_2007_jnl_04.pdf|Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality}}, \\ //IEEE Transactions on Computers//, Vol. 56, No. 11, pp. 1534-1548, November 2007. **(SCI, EI)**  \\ \\ +  - __[[Member:Advisor|Chung-Ho Chen]]__ and Kuo-Su Hsiao, \\ {{research:caslab_2007_jnl_04.pdf|Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality}}, \\ //IEEE Transactions on Computers//, \\ Vol. 56, No. 11, pp. 1534-1548, November 2007. **(SCI, EI)**  \\ \\ 
-  - __[[Member:Advisor|Chung-Ho Chen]]__, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao, \\ {{research:caslab_2007_jnl_02.pdf|Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 15, No. 5, pp. 505-517, May 2007. **(SCI, EI)**  \\ \\ +  - __[[Member:Advisor|Chung-Ho Chen]]__, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao, \\ {{research:caslab_2007_jnl_02.pdf|Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 15, No. 5, pp. 505-517, May 2007. **(SCI, EI)**  \\ \\ 
-  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_jnl_01.pdf|Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 14, No. 10, pp. 1089-1102, October 2006. **(SCI, EI)**  \\ \\ +  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_jnl_01.pdf|Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 14, No. 10, pp. 1089-1102, October 2006. **(SCI, EI)**  \\ \\ 
-  - __[[member:advisor|C. -H. Chen]]__ and F.-F Lin, \\ {{research:caslab_1999_jnl_02.pdf|An Easy-to-Use Approach for Practical Bus-Based System Design}}, \\ //IEEE Transactions on Computers//, Vol. 48, No. 8, pp. 780-793, August 1999. 國科會甲種研究獎 (SCI, EI) \\ \\ +  - __[[member:advisor|C. -H. Chen]]__ and F.-F Lin, \\ {{research:caslab_1999_jnl_02.pdf|An Easy-to-Use Approach for Practical Bus-Based System Design}}, \\ //IEEE Transactions on Computers//, \\ Vol. 48, No. 8, pp. 780-793, August 1999. 國科會甲種研究獎 (SCI, EI) \\ \\ 
-  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1999_jnl_01.pdf|Fault-Containment in Cache Memories for TMR Redundant Processor Systems}}, \\ //IEEE Transactions on Computers//, Vol. 48, No. 4, pp. 386-39, April 1999. 國科會甲種研究獎 (SCI, EI) \\ \\ +  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1999_jnl_01.pdf|Fault-Containment in Cache Memories for TMR Redundant Processor Systems}}, \\ //IEEE Transactions on Computers//, \\ Vol. 48, No. 4, pp. 386-39, April 1999. 國科會甲種研究獎 (SCI, EI) \\ \\ 
-  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1996_jnl_02.pdf|Architecture Technique Trade-Offs Using Mean Memory Delay Time}}, \\ //IEEE Transactions on Computers//, Vol. 45, No. 10, pp. 1089-1100, October 1996. 國科會甲種研究獎 (SCI, EI) \\ \\ +  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1996_jnl_02.pdf|Architecture Technique Trade-Offs Using Mean Memory Delay Time}}, \\ //IEEE Transactions on Computers//, \\ Vol. 45, No. 10, pp. 1089-1100, October 1996. 國科會甲種研究獎 (SCI, EI) \\ \\ 
-  - Craig M. Wittenbrink, A. K. Somani, and __[[member:advisor|C. -H. Chen]]__, \\ {{research:caslab_1996_jnl_01.pdf|Cache Write Generate for Parallel Image Processing on Shared Memory Architectures}}, \\ //IEEE Transactions on Image Processing//, Vol. 5, No. 7, pp. 1204-1208, July 1996. (SCI, EI) \\ \\ +  - Craig M. Wittenbrink, A. K. Somani, and __[[member:advisor|C. -H. Chen]]__, \\ {{research:caslab_1996_jnl_01.pdf|Cache Write Generate for Parallel Image Processing on Shared Memory Architectures}}, \\ //IEEE Transactions on Image Processing//, \\ Vol. 5, No. 7, pp. 1204-1208, July 1996. (SCI, EI) \\ \\ 
-  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1994_jnl_01.pdf|A Unified Architectural Tradeoff Methodology}}, \\ //ACM SIGARCH Computer Architecture News//, Vol. 22, Iss. 2, pp. 348-357, April 1994.+  - __[[member:advisor|C. -H. Chen]]__ and A. K. Somani, \\ {{research:caslab_1994_jnl_01.pdf|A Unified Architectural Tradeoff Methodology}}, \\ //ACM SIGARCH Computer Architecture News//, \\ Vol. 22, Iss. 2, pp. 348-357, April 1994.
  
-==== Other Journal Paper (10) ====+==== 其他期刊論文 (10) ====
   - __[[Member:jay|Chen-Chieh Wang]]__, and__[[Member:Advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2013_jnl_01.pdf|A System‐Level Network Virtual Platform for IPsec Processor Development}}, \\ //IEICE Transactions on Information and Systems//, \\ Vol.E96-D, No.5, pp.1095-1104, May 2013. **(SCI, EI)** \\ \\   - __[[Member:jay|Chen-Chieh Wang]]__, and__[[Member:Advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2013_jnl_01.pdf|A System‐Level Network Virtual Platform for IPsec Processor Development}}, \\ //IEICE Transactions on Information and Systems//, \\ Vol.E96-D, No.5, pp.1095-1104, May 2013. **(SCI, EI)** \\ \\
   - __ Chung-Ming Chen__, and__[[Member:Advisor|Chung-Ho Chen]]__, \\ Window Architecture for Deblocking Filter in H.264/AVC, \\ //International Journal of Innovative Computing, Information and Control//, \\ Vol. 3, No. 6, pp. 1677-1695, December 2007. **(SCI, EI)** \\ \\   - __ Chung-Ming Chen__, and__[[Member:Advisor|Chung-Ho Chen]]__, \\ Window Architecture for Deblocking Filter in H.264/AVC, \\ //International Journal of Innovative Computing, Information and Control//, \\ Vol. 3, No. 6, pp. 1677-1695, December 2007. **(SCI, EI)** \\ \\
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 \\ \\
-===== International Conference Paper (50) ===== +===== 會議論文 ===== 
-----+==== 國際會議論文 (50) ==== 
 +  - Yun-Chi Huang, Kuan-Chieh Hsu, Wan-shan Hsieh, Chen-Chieh Wang, Chia-Han Lu and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2016_cnf_01.pdf|Dynamic SIMD re-convergence with paired-path comparison}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)//, \\ May 22-25, 2016, Montreal, Canada.  \\ \\ 
 +  - Chun-Po Huang, Ya-Ting Shyu, Tsung-Yu Hsieh, Chieh-Wen Cheng, Wei-Chiun Liu, Hao-Ting Jian, Ying-Wei Wang, Bin-Da Liu, Soon-Jyh Chang, Lih-Yih Chiou and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2015_cnf_03.pdf|The SoC design of a versatile biomedical signal processor for potentiostat}}, \\ //in the International Bioelectronics and Bioinformatics Conference (ISBB)//, \\ Oct 14-17, 2015, Beijing, China.  \\ \\ 
 +  - Chien-Hsuan Yen, __[[Member:Advisor|Chung-Ho Chen]]__ and Kuan-Chung Chen, \\ {{:research:caslab_2015_cnf_01.pdf|A memory-efficient NoC system for OpenCL many-core platform}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)//, \\ May 24-27, 2015, Lisbon, Portugal.  \\ \\ 
 +  - Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2014_cnf_03.pdf|An OpenCL runtime system for a heterogeneous many-core virtual platform}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)//, \\ June 1-5, 2014, Melbourne VIC, Australia.  \\ \\
   - __[[en:member:elvis|Jhe-Yu Liou]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_01.pdf|Re-visit Blocking Texture Cache Design for Modern GPU}}, \\ //in the 11th International SoC Design Conference (ISOCC)//, \\ Nov. 3-6, 2014, Jeju, Korea. \\ \\   - __[[en:member:elvis|Jhe-Yu Liou]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_01.pdf|Re-visit Blocking Texture Cache Design for Modern GPU}}, \\ //in the 11th International SoC Design Conference (ISOCC)//, \\ Nov. 3-6, 2014, Jeju, Korea. \\ \\
-  - Tzu-Hsuan Hsu, Ching-Wen Lin and __[[member:advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2013_cnf_02.pdf|Using Condition Flag Prediction to Improve the Performance of Out-of-Order Processors}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)// , \\ May 19-23, 2013 ,National Cheng Kung University, Tainan, Taiwan. \\ \\ +  - Tzu-Hsuan Hsu, Ching-Wen Lin and __[[member:advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2013_cnf_02.pdf|Using Condition Flag Prediction to Improve the Performance of Out-of-Order Processors}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)// , \\ May 19-23, 2013 , Beijing, China. \\ \\ 
-  - Chien-Te Liu, Kuan-Chung Chen and __[[member:advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2013_cnf_01.pdf|CASL Hypervisor and its Virtualization Platform}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)// , \\ May 19-23, 2013 ,National Cheng Kung University, Tainan, Taiwan.+  - Chien-Te Liu, Kuan-Chung Chen and __[[member:advisor|Chung-Ho Chen]]__, \\ {{:research:caslab_2013_cnf_01.pdf|CASL Hypervisor and its Virtualization Platform}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)// , \\ May 19-23, 2013 , Beijing, China.
   - Hsu-Yao Huang, Chi-Yuan Huang, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|Tile-Based GPU Optimizations through ESL Full System Simulation}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 20-23, 2012, Seoul, Korea.  \\ \\   - Hsu-Yao Huang, Chi-Yuan Huang, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|Tile-Based GPU Optimizations through ESL Full System Simulation}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 20-23, 2012, Seoul, Korea.  \\ \\
   - __[[Member:jay|Chen-Chieh Wang]]__, Sheng-Hsin Lo, Yao-Ning Liu, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 20-23, 2012, Seoul, Korea.  \\ \\   - __[[Member:jay|Chen-Chieh Wang]]__, Sheng-Hsin Lo, Yao-Ning Liu, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 20-23, 2012, Seoul, Korea.  \\ \\
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   - A. K. Somani, C. Wittenbrink, R. M. Haralick, L. G. Shapiro, J. N. Hwang, __[[Member:Advisor|C. -H. Chen]]__, R. Johnson, and K. Cooper, \\ Proteus System Architecture and Organization, \\ //in the Proceeding of the Fifth International Parallel Processing Symposium,// \\ pp. 287-294, 1991.   - A. K. Somani, C. Wittenbrink, R. M. Haralick, L. G. Shapiro, J. N. Hwang, __[[Member:Advisor|C. -H. Chen]]__, R. Johnson, and K. Cooper, \\ Proteus System Architecture and Organization, \\ //in the Proceeding of the Fifth International Parallel Processing Symposium,// \\ pp. 287-294, 1991.
 \\ \\
-===== Local Conference Paper (8) ===== +==== 國內會議論文 (8) ====
-----+
   - Yi-Ying Tsai, Ke-Jia Lee, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_cnf_07.pdf|Code Compression Architecture for Memory Bandwidth Optimization in Embedded Systems}}, \\ //in the Proceeding of the International Computer Symposium (ICS)//, 2006, Taiwan.  \\ \\   - Yi-Ying Tsai, Ke-Jia Lee, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_cnf_07.pdf|Code Compression Architecture for Memory Bandwidth Optimization in Embedded Systems}}, \\ //in the Proceeding of the International Computer Symposium (ICS)//, 2006, Taiwan.  \\ \\
   - Po-Kai Chan, __[[Member:Advisor|Chung-Ho Chen]]__, and Cheng-Yeh Yu, \\ An iWARP-Based TCP/IP Offload Engine, \\ //in the Proceeding of the 17th VLSI Design/CAD Symposium//, August 8-11, 2006.  \\ \\   - Po-Kai Chan, __[[Member:Advisor|Chung-Ho Chen]]__, and Cheng-Yeh Yu, \\ An iWARP-Based TCP/IP Offload Engine, \\ //in the Proceeding of the 17th VLSI Design/CAD Symposium//, August 8-11, 2006.  \\ \\
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 \\ \\
 ===== 著書 ===== ===== 著書 =====
----- 
   - 嵌入式系統設計 - 以 ARM 處理器基礎之 SOC 平台， \\ 黃悅民、[[http://office.ee.ncku.edu.tw/nckueechinese/professor/T210-jchen/T0000000c.htm|陳敬]]、侯廷偉、__[[member:advisor|陳中和]]__、黃慶祥、林志敏編著。 \\ ISBN 986-7287-63-0 滄海書局， March 2006. \\ 獲評選為優良教科書，教育部顧問室通訊科技人才培育先導型計畫寬頻網際網路組， \\ 台顧字第 0950179468 號 。 \\ \\   - 嵌入式系統設計 - 以 ARM 處理器基礎之 SOC 平台， \\ 黃悅民、[[http://office.ee.ncku.edu.tw/nckueechinese/professor/T210-jchen/T0000000c.htm|陳敬]]、侯廷偉、__[[member:advisor|陳中和]]__、黃慶祥、林志敏編著。 \\ ISBN 986-7287-63-0 滄海書局， March 2006. \\ 獲評選為優良教科書，教育部顧問室通訊科技人才培育先導型計畫寬頻網際網路組， \\ 台顧字第 0950179468 號 。 \\ \\
   - TCP/IP 通訊協定 ( 第三版 )， \\ __[[member:advisor|陳中和]]__、__[[member:jay|王振傑]]__譯。 \\ The McGraw-Hill Companies Inc., \\ ISBN-13: 978-986-157-321-2, Nov. 2006. \\ \\   - TCP/IP 通訊協定 ( 第三版 )， \\ __[[member:advisor|陳中和]]__、__[[member:jay|王振傑]]__譯。 \\ The McGraw-Hill Companies Inc., \\ ISBN-13: 978-986-157-321-2, Nov. 2006. \\ \\
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 \\ \\
 ===== 專利 ===== ===== 專利 =====
----- 
   - 具多協定處理單位之儲存架構及方法, \\ 中華民國專利 I247991 號, 2006. \\ \\   - 具多協定處理單位之儲存架構及方法, \\ 中華民國專利 I247991 號, 2006. \\ \\
   - Multiprocessor system with write generate method for updating cache, \\ United States patent, No. 5524212, June 1996. \\ \\   - Multiprocessor system with write generate method for updating cache, \\ United States patent, No. 5524212, June 1996. \\ \\
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 ===== 舉辦 ===== ===== 舉辦 =====
----- 
   - 主辦2011 IEEE CASS Workshop on Circuit and System New Curriculum for Interdisciplinary Reform and evelopment   - 主辦2011 IEEE CASS Workshop on Circuit and System New Curriculum for Interdisciplinary Reform and evelopment
   - 2010 年擔任教育部嵌入式系統設計競賽主持人   - 2010 年擔任教育部嵌入式系統設計競賽主持人
member/advisor.1415978717.txt.gz · 上一次變更: 2014/11/14 15:25 由 elvis

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