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-{{Research:Publications201305.png}}+====== 公開著作 ====== 
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 (((c)2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.)) (((c)2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.))
 (((c)2004 ACM. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from Publications Dept, ACM Inc., fax +1 (212) 869-0481, or permissions@acm.org.)) (((c)2004 ACM. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from Publications Dept, ACM Inc., fax +1 (212) 869-0481, or permissions@acm.org.))
  
-====== Journal Publications ====== +===== 期刊論文發表 ===== 
----------------------------------- +  - __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2018_jnl_01.pdf|Enabling SIMT Execution Model on Homogeneous Multi-Core System}}, \\ //ACM Transactions on Architecture and Code Optimization//, \\ Volume 15 Issue 1, April 2018 \\ Article No. 6  \\ \\ 
-  - __En-Hao Chang__, __Chen-Chieh Wang__, __Chien-Te Liu__, __Kuan-Chung Chen__ and [[Member:Advisor|Chung-Ho Chen]], {{research:caslab_2014_jnl_01.pdf|Virtualization Technology for TCP/IP Offload Engine}}, IEEE Transactions on Cloud Computing, February 2014. (Accepted) (SCI, EI)   +  - __[[Member:klio|Ching-Wen Lin]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2017_jnl_01.pdf|A Processor and Cache Online Self-Testing Methodology for OS-Managed Platform}}, \\ //IEEE Transactions on Very Large Scale Integration (VLSI) Systems//, \\ Vol. 25, No. 8, pp. 2346-2359, August 2017. \\ \\ 
-  - __Chen-Chieh Wang__ and [[Member:Advisor|Chung-Ho Chen]], {{research:caslab_2013_jnl_01.pdf|A System‐Level Network Virtual Platform for IPsec Processor Development}}, IEICE Transactions on Information and Systems, Vol.E96-D, No.5, pp.1095-1104, May 2013. (SCI, EI) +  - __En-Hao Chang__, __[[Member:jay|Chen-Chieh Wang]]__, __Chien-Te Liu__, __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_jnl_01.pdf|Virtualization Technology for TCP/IP Offload Engine}}, \\ //IEEE Transactions on Cloud Computing//, \\ Vol. 2, No. 2, April-June 2014. **(SCI, EI)** \\ \\ 
-  - __Yi-Ying Tsai__ and [[Member:Advisor|Chung-Ho Chen]], {{research:caslab_2011_jnl_02.pdf|Energy-efficient Trace Reuse Cache for Embedded Processor}}, IEEE Transactions on Very Large Scale Integration Systems, Vol. 19, No. 9, pp. 1681-1694, September 2011. (SCI, EI) +  - __[[Member:jay|Chen-Chieh Wang]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_jnl_01.pdf|A System‐Level Network Virtual Platform for IPsec Processor Development}}, \\ //IEICE Transactions on Information and Systems//, \\ Vol.E96-D, No.5, pp.1095-1104, May 2013. **(SCI, EI)**  \\ \\ 
-  - Tai-Hua Lu, [[Member:Advisor|Chung-Ho Chen]], and Kuen-Jong Lee, {{research:caslab_2011_jnl_01.pdf|Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores}}, IEEE Transactions on Very Large Scale Integration Systems, Vol. 19, No. 3, pp. 516-520, March 2011. (SCI, EI) +  - __Yi-Ying Tsai__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2011_jnl_02.pdf|Energy-efficient Trace Reuse Cache for Embedded Processor}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 19, No. 9, pp. 1681-1694, September 2011. **(SCI, EI)**  \\ \\ 
-  - Wei-Cheng Lin and [[Member:Advisor|Chung-Ho Chen]], Frame Buffer Access Reduction for MPEG Video Decoder, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 18, No. 10, pp. 1452-1456, October 2008. (SCI, EI) +  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2011_jnl_01.pdf|Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 19, No. 3, pp. 516-520, March 2011. **(SCI, EI)**  \\ \\ 
-  - Chung-Ming Chen and Chung-Ho Chen, Configurable VLSI Architecture for Deblocking Filter in H.264/AVC, IEEE Transactions on Very Large Scale Integration Systems, Vol. 16, No. 8, pp. 1072-1082, August 2008. (SCI, EI)  +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_02.pdf|Frame Buffer Access Reduction for MPEG Video Decoder}}, \\ //IEEE Transactions on Circuits and Systems for Video Technology//, \\ Vol. 18, No. 10, pp. 1452-1456, October 2008. **(SCI, EI)**  \\ \\ 
-  - Chung-Ming Chen and Chung-Ho Chen, Window Architecture for Deblocking Filter in H.264/AVC, International Journal of Innovative Computing, Information and Control, Vol. 3, No. 6, pp. 1677-1695, December 2007. (SCI, EI)  +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_01.pdf|Configurable VLSI Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 16, No. 8, pp. 1072-1082, August 2008. **(SCI, EI)**   \\ \\ 
-  - Chung-Ho Chen and Kuo-Su Hsiao, Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality, IEEE Transactions on Computers, Vol. 56, No. 11, pp. 1534-1548, November 2007.(SCI, EI) +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ Window Architecture for Deblocking Filter in H.264/AVC, \\ //International Journal of Innovative Computing//, Information and Control, \\ Vol. 3, No. 6, pp. 1677-1695, December 2007. **(SCI, EI)**  \\ \\ 
-  - Chung-Ho Chen, Chao-Hsien Hsu, and Chen-Chieh Wang, Scalable IPv6 Lookup/Update Design for High-Throughput Routers, Journal of Internet Technology, Vol. 8, No. 3, pp. 261-269, July 2007. (EI) +  - __[[Member:Advisor|Chung-Ho Chen]]__ and Kuo-Su Hsiao, \\ {{research:caslab_2007_jnl_04.pdf|Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality}}, \\ //IEEE Transactions on Computers//, \\ Vol. 56, No. 11, pp. 1534-1548, November 2007. **(SCI, EI)**  \\ \\ 
-  - Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao, Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores, IEEE Transactions on Very Large Scale Integration Systems, Vol. 15, No. 5, pp. 505-517, May 2007. (SCI, EI) +  - __[[Member:Advisor|Chung-Ho Chen]]__, Chao-Hsien Hsu, and __[[Member:jay|Chen-Chieh Wang]]__, \\ {{research:caslab_2007_jnl_03.pdf|Scalable IPv6 Lookup/Update Design for High-Throughput Routers}}, \\ //Journal of Internet Technology//, \\ Vol. 8, No. 3, pp. 261-269, July 2007. **(EI)**  \\ \\ 
-  - Chung-Ming Chen and Chung-Ho Chen, An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC, IEICE Transactions on Information and Systems, Vol. E90-D, No.1 pp.99-107, January 2007. (SCI, EI) +  - __[[Member:Advisor|Chung-Ho Chen]]__, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao, \\ {{research:caslab_2007_jnl_02.pdf|Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 15, No. 5, pp. 505-517, May 2007. **(SCI, EI)**  \\ \\ 
-  - Kuo-Su Hsiao and Chung-Ho Chen, Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation, IEEE Transactions on Very Large Scale Integration Systems, Vol. 14, No. 10, pp. 1089-1102, October 2006. (SCI, EI) +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2007_jnl_01.pdf|An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEICE Transactions on Information and Systems//, \\ Vol. E90-D, No.1 pp.99-107, January 2007. **(SCI, EI)**  \\ \\ 
-  - M.-D. Shieh, M.-H. Sheu, C.-H. Chen , and H.-F. Lo A Systematic Approach for Parallel CRC Computations, Journal of Information Science and Engineering, Vol. 17, No. 3, pp. 445-461, May 2001. (SCI) +  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_jnl_01.pdf|Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 14, No. 10, pp. 1089-1102, October 2006. **(SCI, EI)**  \\ \\ 
-  - C.-H. Chen and Akida Wu, Address Prediction Using a Bit-Matrix Indexing Scheme for Selective Update, Journal of Computers, Vol. 12 No.3, September 2000. +  - M.-D. Shieh, M.-H. Sheu, __[[Member:Advisor|C.-H. Chen]]__ , and H.-F. Lo, \\ {{research:caslab_2001_jnl_01.pdf|A Systematic Approach for Parallel CRC Computations}}, \\ //Journal of Information Science and Engineering//, \\ Vol. 17, No. 3, pp. 445-461, May 2001. **(SCI)**  \\ \\ 
-  - C.-H. Chen and Akida Wu, Performance Evaluation of Load/Store Issue and Memory Access Policies, Journal of the Chinese Institute of Engineers, Vol.23, No. 6, pp. 697-709, 2000. (SCI, EI) +  - __[[Member:Advisor|C.-H. Chen]]__ and Akida Wu, \\ Address Prediction Using a Bit-Matrix Indexing Scheme for Selective Update, \\ //Journal of Computers//, \\ Vol. 12 No.3, September 2000.  \\ \\ 
- +  - __[[Member:Advisor|C.-H. Chen]]__ and Akida Wu, \\ Performance Evaluation of Load/Store Issue and Memory Access Policies, \\ //Journal of the Chinese Institute of Engineers//, \\ Vol.23, No. 6, pp. 697-709, 2000. **(SCI, EI)**
  
 +\\
 +===== 會議論文發表 =====
 +  - J.-W. Lin , and ____[[Member:Advisor|Chung-Ho Chen]]____,\\ {{research:caslab_2017_cnf_01.pdf|  Processor Shield for L1 Data Cache Software-Based On-line Self-testing}}, \\ //in Asia South Pacific Des. Autom. Conf.//  , \\ January 16-19, 2017, Japan \\ \\
 +  - J.-W. Lin , and ____[[Member:Advisor|Chung-Ho Chen]]____,\\ {{research:caslab_2016_cnf_02.pdf| A Processor Shield for Software-Based On-Line Self-Test}}, \\ //in IEEE Asia Pacific Conf. Circuits and Systems//, \\ October 25-28, 2016, Korea \\ \\
 +  - Yun-Chi Huang, Kuan-Chieh Hsu, Wan-shan Hsieh, Chen-Chieh Wang, Chia-Han Lu, and __[[Member:Advisor|Chung-Ho Chen]]___,\\ {{research:caslab_2016_cnf_01.pdf|Dynamic SIMD Re-convergence with Paired-Path Comparison }}  , \\ //in the 2016 IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 23-25, 2016, Montreal, Canada. \\ \\
 +  - Yung Hsu and __ __[[Member:Advisor|Chung-Ho Chen]]____, \\ {{research:caslab_2015_cnf_02.pdf|A Heterogeneous System Architecture Conformed GPU Platform Supporting OpenCL and OpenGL}}, \\ //Taiwan and Japan Conference on Circuits and Systems (TJCAS)//, \\ Aug. 18-23, 2015, Japan \\ \\
 +  - Heng-Yi Chen,__ __ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{|An HSAIL ISA Conformed GPU Platform}}, \\ //In International Conference on Innovation, Communication and Engineering (ICICE)//, \\  Oct 23-28. 2015. Xiangtan, Hunan, P.R. China\\ \\
 +  - Chien-Hsuan Yen, Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2015_cnf_01.pdf|A memory-efficient NoC system for OpenCL many-core platform}}, \\ //in the 2015 IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 24-27, 2015, Lisbon, Portugal. \\ \\ 
 +  - Ching-Wen Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_02.pdf|Unambiguous I-cache testing using software-based self-testing methodology}}, \\ //in the 2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ June 1-5, 2014 ,Melbourne VIC, Australian. \\ \\
 +  - Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_03.pdf|An OpenCL Runtime System for a Heterogeneous many-Core Virtual Platform }}, \\ //in the 2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ June 1-5, 2014 ,Melbourne VIC, Australian. \\ \\
 +  - __[[en:member:elvis|Jhe-Yu Liou]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_01.pdf|Re-visit Blocking Texture Cache Design for Modern GPU}}, \\ //in the 11th International SoC Design Conference (ISOCC)//, \\ Nov. 3-6, 2014, Jeju, Korea. \\ \\
 +  - Tzu-Hsuan Hsu, Ching-Wen Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_cnf_02.pdf|Using Condition Flag Prediction to Improve the Performance of Out-of-Order Processors}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 19-23, 2013 ,Beijing, China. \\ \\
 +  - Chien-Te Liu, Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_cnf_01.pdf|CASL Hypervisor and its Virtualization Platform}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 19-23, 2013 ,Beijing, China. \\ \\
 +  - Hsu-Yao Huang, Chi-Yuan Huang, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_01.pdf|Tile-Based GPU Optimizations through ESL Full System Simulation}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 20-23, 2012, Seoul, Korea.  \\ \\
 +  - __[[Member:jay|Chen-Chieh Wang]]__, Sheng-Hsin Lo, Yao-Ning Liu, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 20-23, 2012, Seoul, Korea.  \\ \\
 +  - __[[Member:jay|Chen-Chieh Wang]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ An Optimized Cryptographic Processing Unit for IPsec Processors, \\ //in the 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)//, \\ June 19-22, 2011, Gyeongju, Korea.  \\ \\
 +  - Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ A Synchronization Profiler for Hybrid Full System Simulation Platform, \\ //in the International SoC Design Conference (ISOCC-2010)//, \\ Nov. 22-23, 2010, Incheon, Korea.  \\ \\
 +  - Xie-Zeng Shen, Shin-Ying Lee, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2010_cnf_01.pdf|Full System Simulation with QEMU: an Approach to Multi-View 3D GPU Design}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 30 - June 2, 2010, Paris, France.  \\ \\
 +  - Jing-Wun Lin, __[[Member:jay|Chen-Chieh Wang]]__, Chin-Yao Chang, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2009_cnf_02.pdf|Full System Simulation and Verification Framework}}, \\ //in the Proceedings of the Fifth International Conference on Information Assurance and Security (IAS-2009)//, \\ August 18-20, 2009, Xi'an, China.  \\ \\
 +  - __[[Member:jay|Chen-Chieh Wang]]__, Ro-Pun Wong, Jing-Wun Lin, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2009_cnf_01.pdf|System-Level Development and Verification Framework for High-Performance System Accelerator}}, \\ //in the IEEE International Symposium on VLSI Design//, Automation & Test (VLSI-DAT), \\ April 27-30, 2009, Hsinchu, Taiwan.  \\ \\
 +  - Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_cnf_06.pdf|A Software-Based Test Methodology for Direct-Mapped Data Cache}}, \\ //in the IEEE Seventeenth Asian Test Symposium (ATS)//, November 24-27, 2008, Sapporo, Japan.  \\ \\
 +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_cnf_05.pdf|Avoiding Unnecessary Frame Memory Access and Multi-Frame Motion Estimation Computation in H.264/AVC}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, May 18-21, 2008, Seattle, Washington, USA. \\ \\
 +  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2008_cnf_04.pdf|A Hybrid Self-Testing methodology of Processor Cores}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, May 18-21, 2008, Seattle, Washington, USA.  \\ \\
 +  - Yi-Ying Tsai, Chia-Jung Hsu, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_cnf_03.pdf|Address Compression for Scalable Load/Store Queue Implementation}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, May 18-21, 2008, Seattle, Washington, USA.  \\ \\
 +  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2008_cnf_02.pdf|A Hybrid Software-Based Self-Testing methodology for Embedded Processor}}, \\ //in the ACM Symposium on Applied Computing (SAC)//, March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)  \\ \\
 +  - Yi-Ying Tsai, Chia-Jung Hsu, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_cnf_01.pdf|Power-efficient and Scalable Load/Store Queue Design via Address Compression}}, \\ //in the ACM Symposium on Applied Computing (SAC)//, March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)  \\ \\
 +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2007_cnf_03.pdf|A Data-Reuse Scheme for Avoiding Unnecessary Frame Buffer Accesses and Display RAM Accesses in MPEG-4 ASP Video Decoder}}, \\ //in the IEEE International SoC Conference (SOCC)//, September 26-29, 2007, Hsinchu, Taiwan.  \\ \\
 +  - Yi-Cheng Chung, Stanley Lee, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2007_cnf_02.pdf|A Packet Forwarding Method for the iSCSI Virtualization Switch}}, \\ //in the 4th International Workshop on Storage Network Architecture and Parallel I/Os (SNAPI)//, September 24, 2007, San Diego, California, USA.  \\ \\
 +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2007_cnf_01.pdf|Reduction of Frame Memory Accesses and Motion Estimation Computations in MPEG-4 Video Encoder}}, \\ //in the 16th International Conference on Computer Communications and Networks (ICCCN)//, August 13-16, 2007, Honolulu, Hawaii, USA.  \\ \\
 +  - __[[Member:Advisor|Chung-Ho Chen]]__, Yi-Cheng Chung, Chen-Hua Wang, and Han-Chiang Chen, \\ {{research:caslab_2006_cnf_01.pdf|Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator}}, \\ //in the 31st Annual IEEE Conference on Local Computer Networks (LCN)//, November 14-16, 2006, Tampa, Florida, USA.  \\ \\
 +  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_cnf_02.pdf|Scheduler Optimization by Exploring Wakeup Locality}}, \\ //in the International Conference of Computer Engineering & Systems (ICCES)//, November 5-7, 2006, Egypt.  \\ \\
 +  - Chung-Ming Chen, __[[Member:Advisor|Chung-Ho Chen]]__, Jian-Ping Zeng, and Chao-Tang Yu, \\ {{research:caslab_2006_cnf_03.pdf|Windows Processing for Deblocking Filter in H.264/AVC}}, \\ //in the Proceeding of the 32nd Annual Conference of the IEEE Industrial Electronics (IECON)//, November 7-10, 2006, Paris, France.  \\ \\
 +  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_cnf_04.pdf|Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling}}, \\ //in the International Conference of Computer Design//, October, 2006, USA. (EI)  \\ \\
 +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_cnf_05.pdf|Exploring Reusable Frame Buffer Data for MPEG-4 Video Decoding}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, 2006, Island of Kos, Greece. (EI)  \\ \\
 +  - Chung-Ming Chen, Jian-Ping Zeng, __[[Member:Advisor|Chung-Ho Chen]]__, Chao-Tang Yu, and Yu-Pin Chang, \\ {{research:caslab_2006_cnf_06.pdf|Window Architecture for Deblocking Filter in H.264/AVC}}, \\ //in the 6th IEEE International Symposium on Signal Processing and Information Technology//, August 27-30, 2006, Vancouver, Canada. (EI)  \\ \\
 +  - Yi-Ying Tsai, Ke-Jia Lee, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_cnf_07.pdf|Code Compression Architecture for Memory Bandwidth Optimization in Embedded Systems}}, \\ //in the Proceeding of the International Computer Symposium (ICS)//, 2006, Taiwan.  \\ \\
 +  - Po-Kai Chan, __[[Member:Advisor|Chung-Ho Chen]]__, and Cheng-Yeh Yu, \\ An iWARP-Based TCP/IP Offload Engine, \\ //in the Proceeding of the 17th VLSI Design/CAD Symposium//, August 8-11, 2006.  \\ \\
 +  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2005_cnf_01.pdf|An Efficient Wakeup Design for Energy Reduction in High-Performance Superscalar Processors}}, \\ //in the ACM SIGMicro International Conference on Computing Frontiers (CF)//, 2005, Italy. (EI)  \\ \\
 +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2005_cnf_02.pdf|A Memory Efficient Architecture for Deblocking Filter in H.264 Using Vertical Processing Order}}, \\ //in the IEEE International Conference on Intelligent Sensors, Sensor Networks, and Information Processing (ISSNIP)//, 2005, Australia.  \\ \\
 +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2005_cnf_03.pdf|Parallel Processing for Deblocking Filter in H.264/AVC}}, \\ //in the International Conference on Communications, Internet and Information Technology (CIIT)//, 2005, Cambridge, USA. (EI)  \\ \\
 +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2005_cnf_04.pdf|Alternative Processing Order with Efficient Architecture for Adaptive Deblocking Filter in H.264/AVC}}, \\ //in the International Conference on Communications, Internet, and Information Technology (CIIT)//, 2005, Cambridge, USA. (EI)  \\ \\
 +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2005_cnf_05.pdf|An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding}}, \\ //in the International Conference on Computer Graphics and Imaging (CGIM)//, 2005, Honolulu, Hawaii, USA. (EI)  \\ \\
 +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2005_cnf_06.pdf|An Efficient VLSI Architecture for Edge Filtering in H.264/AVC}}, \\ //in the International Conference on Circuits, Signals, and Systems//, 2005, Marina del Rey, CA, USA.  \\ \\
 +  - F.-M Huang and __[[Member:Advisor|C.-H. Chen]]__, \\ Memory Access Scheduling and Bank Precharge Strategies, \\ //in the poster proceeding of 12 th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems//, 2004, Netherlands.  \\ \\
 +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2004_cnf_02.pdf|An Energy-Delay Efficient Power Management Scheme for Embedded System in Multimedia Applications}}, \\ //in Proceedings of The IEEE Asia Pacific Conference on Circuit & System (APCCAS)//,2004, Taiwan. (EI)  \\ \\
 +  - N.-Y. Ker, and __[[Member:Advisor|C.-H. Chen]]__, \\ An Effective SDRAM Power Mode Management Scheme for Performance and Energy Sensitive Embedded Systems, \\ //in the Proceeding of Asia and South Pacific Design Automation Conference (ASP-DAC)//, 2003, Japan.  \\ \\
 +  - W.-Z. Lin, and __[[Member:Advisor|C.-H. Chen]]__, \\ 10/100/1000 Mbps Ethernet MAC with Clock Management for AMBA System, \\ //in the Proceeding of the 13th VLSI Design/CAD Symposium//, 2002.  \\ \\
 +  - 盧偉聖、__[[Member:Advisor|陳中和]]__、蔡宜穎、林宇峰, \\ The Design of a Digital Control Technology for Lighting and Special Effects, \\ //in the Proceeding of Taiwan Power Electronic Conference//, 2002.  \\ \\
 +  - __[[Member:Advisor|C.-H. Chen]]__, M.-D. Shieh, and Jimmy Shou, \\ VLSI Architecture of an Instruction-Based Crypto Coprocessor, \\ //in the Proceeding of the 11th VLSI Design/CAD Symposium//, 2000.
  
 +{{tabinclude>tab:research|研究成果,tab:group|研究群組,tab:member|實驗室成員,tab:course|課程}}
research/publication.1403943125.txt.gz · 上一次變更: 2014/11/10 02:36 (外部編輯)

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