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research:publication [2014/10/10 13:40]
jay [會議論文發表] 		research:publication [2018/04/17 13:26]
admin
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 ===== 期刊論文發表 ===== ===== 期刊論文發表 =====
----------------------------------- +  - __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2018_jnl_01.pdf|Enabling SIMT Execution Model on Homogeneous Multi-Core System}}, \\ //ACM Transactions on Architecture and Code Optimization//, \\ Volume 15 Issue 1, April 2018 \\ Article No. 6  \\ \\ 
-  - __En-Hao Chang__, __[[Member:jay|Chen-Chieh Wang]]__, __Chien-Te Liu__, __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_jnl_01.pdf|Virtualization Technology for TCP/IP Offload Engine}}, \\ //IEEE Transactions on Cloud Computing//, Vol. 2, No. 2, April-June 2014. **(SCI, EI)** \\ \\+  - __[[Member:klio|Ching-Wen Lin]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2017_jnl_01.pdf|A Processor and Cache Online Self-Testing Methodology for OS-Managed Platform}}, \\ //IEEE Transactions on Very Large Scale Integration (VLSI) Systems//, \\ Vol. 25, No. 8, pp. 2346-2359, August 2017. \\ \\ 
 +  - __En-Hao Chang__, __[[Member:jay|Chen-Chieh Wang]]__, __Chien-Te Liu__, __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_jnl_01.pdf|Virtualization Technology for TCP/IP Offload Engine}}, \\ //IEEE Transactions on Cloud Computing//, \\ Vol. 2, No. 2, April-June 2014. **(SCI, EI)** \\ \\
   - __[[Member:jay|Chen-Chieh Wang]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_jnl_01.pdf|A System‐Level Network Virtual Platform for IPsec Processor Development}}, \\ //IEICE Transactions on Information and Systems//, \\ Vol.E96-D, No.5, pp.1095-1104, May 2013. **(SCI, EI)**  \\ \\   - __[[Member:jay|Chen-Chieh Wang]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_jnl_01.pdf|A System‐Level Network Virtual Platform for IPsec Processor Development}}, \\ //IEICE Transactions on Information and Systems//, \\ Vol.E96-D, No.5, pp.1095-1104, May 2013. **(SCI, EI)**  \\ \\
-  - __Yi-Ying Tsai__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2011_jnl_02.pdf|Energy-efficient Trace Reuse Cache for Embedded Processor}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 19, No. 9, pp. 1681-1694, September 2011. **(SCI, EI)**  \\ \\ +  - __Yi-Ying Tsai__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2011_jnl_02.pdf|Energy-efficient Trace Reuse Cache for Embedded Processor}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 19, No. 9, pp. 1681-1694, September 2011. **(SCI, EI)**  \\ \\ 
-  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2011_jnl_01.pdf|Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 19, No. 3, pp. 516-520, March 2011. **(SCI, EI)**  \\ \\ +  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2011_jnl_01.pdf|Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 19, No. 3, pp. 516-520, March 2011. **(SCI, EI)**  \\ \\ 
-  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_02.pdf|Frame Buffer Access Reduction for MPEG Video Decoder}}, \\ //IEEE Transactions on Circuits and Systems for Video Technology//, Vol. 18, No. 10, pp. 1452-1456, October 2008. **(SCI, EI)**  \\ \\ +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_02.pdf|Frame Buffer Access Reduction for MPEG Video Decoder}}, \\ //IEEE Transactions on Circuits and Systems for Video Technology//, \\ Vol. 18, No. 10, pp. 1452-1456, October 2008. **(SCI, EI)**  \\ \\ 
-  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_01.pdf|Configurable VLSI Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 16, No. 8, pp. 1072-1082, August 2008. **(SCI, EI)**   \\ \\ +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_01.pdf|Configurable VLSI Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 16, No. 8, pp. 1072-1082, August 2008. **(SCI, EI)**   \\ \\ 
-  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ Window Architecture for Deblocking Filter in H.264/AVC, \\ //International Journal of Innovative Computing//, Information and Control, Vol. 3, No. 6, pp. 1677-1695, December 2007. **(SCI, EI)**  \\ \\ +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ Window Architecture for Deblocking Filter in H.264/AVC, \\ //International Journal of Innovative Computing//, Information and Control, \\ Vol. 3, No. 6, pp. 1677-1695, December 2007. **(SCI, EI)**  \\ \\ 
-  - __[[Member:Advisor|Chung-Ho Chen]]__ and Kuo-Su Hsiao, \\ {{research:caslab_2007_jnl_04.pdf|Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality}}, \\ IEEE Transactions on Computers, Vol. 56, No. 11, pp. 1534-1548, November 2007. **(SCI, EI)**  \\ \\ +  - __[[Member:Advisor|Chung-Ho Chen]]__ and Kuo-Su Hsiao, \\ {{research:caslab_2007_jnl_04.pdf|Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality}}, \\ //IEEE Transactions on Computers//, \\ Vol. 56, No. 11, pp. 1534-1548, November 2007. **(SCI, EI)**  \\ \\ 
-  - __[[Member:Advisor|Chung-Ho Chen]]__, Chao-Hsien Hsu, and __[[Member:jay|Chen-Chieh Wang]]__, \\ {{research:caslab_2007_jnl_03.pdf|Scalable IPv6 Lookup/Update Design for High-Throughput Routers}}, \\ //Journal of Internet Technology//, Vol. 8, No. 3, pp. 261-269, July 2007. **(EI)**  \\ \\ +  - __[[Member:Advisor|Chung-Ho Chen]]__, Chao-Hsien Hsu, and __[[Member:jay|Chen-Chieh Wang]]__, \\ {{research:caslab_2007_jnl_03.pdf|Scalable IPv6 Lookup/Update Design for High-Throughput Routers}}, \\ //Journal of Internet Technology//, \\ Vol. 8, No. 3, pp. 261-269, July 2007. **(EI)**  \\ \\ 
-  - __[[Member:Advisor|Chung-Ho Chen]]__, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao, \\ {{research:caslab_2007_jnl_02.pdf|Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 15, No. 5, pp. 505-517, May 2007. **(SCI, EI)**  \\ \\ +  - __[[Member:Advisor|Chung-Ho Chen]]__, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao, \\ {{research:caslab_2007_jnl_02.pdf|Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 15, No. 5, pp. 505-517, May 2007. **(SCI, EI)**  \\ \\ 
-  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2007_jnl_01.pdf|An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEICE Transactions on Information and Systems//, Vol. E90-D, No.1 pp.99-107, January 2007. **(SCI, EI)**  \\ \\ +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2007_jnl_01.pdf|An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEICE Transactions on Information and Systems//, \\ Vol. E90-D, No.1 pp.99-107, January 2007. **(SCI, EI)**  \\ \\ 
-  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_jnl_01.pdf|Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 14, No. 10, pp. 1089-1102, October 2006. **(SCI, EI)**  \\ \\ +  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_jnl_01.pdf|Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 14, No. 10, pp. 1089-1102, October 2006. **(SCI, EI)**  \\ \\ 
-  - M.-D. Shieh, M.-H. Sheu, __[[Member:Advisor|C.-H. Chen]]__ , and H.-F. Lo, \\ {{research:caslab_2001_jnl_01.pdf|A Systematic Approach for Parallel CRC Computations}}, \\ //Journal of Information Science and Engineering//, Vol. 17, No. 3, pp. 445-461, May 2001. **(SCI)**  \\ \\ +  - M.-D. Shieh, M.-H. Sheu, __[[Member:Advisor|C.-H. Chen]]__ , and H.-F. Lo, \\ {{research:caslab_2001_jnl_01.pdf|A Systematic Approach for Parallel CRC Computations}}, \\ //Journal of Information Science and Engineering//, \\ Vol. 17, No. 3, pp. 445-461, May 2001. **(SCI)**  \\ \\ 
-  - __[[Member:Advisor|C.-H. Chen]]__ and Akida Wu, \\ Address Prediction Using a Bit-Matrix Indexing Scheme for Selective Update, \\ //Journal of Computers//, Vol. 12 No.3, September 2000.  \\ \\ +  - __[[Member:Advisor|C.-H. Chen]]__ and Akida Wu, \\ Address Prediction Using a Bit-Matrix Indexing Scheme for Selective Update, \\ //Journal of Computers//, \\ Vol. 12 No.3, September 2000.  \\ \\ 
-  - __[[Member:Advisor|C.-H. Chen]]__ and Akida Wu, \\ Performance Evaluation of Load/Store Issue and Memory Access Policies, \\ //Journal of the Chinese Institute of Engineers//, Vol.23, No. 6, pp. 697-709, 2000. **(SCI, EI)**+  - __[[Member:Advisor|C.-H. Chen]]__ and Akida Wu, \\ Performance Evaluation of Load/Store Issue and Memory Access Policies, \\ //Journal of the Chinese Institute of Engineers//, \\ Vol.23, No. 6, pp. 697-709, 2000. **(SCI, EI)**
  
 \\ \\
 ===== 會議論文發表 ===== ===== 會議論文發表 =====
-------------------- +  - J.-W. Lin , and ____[[Member:Advisor|Chung-Ho Chen]]____,\\ {{research:caslab_2017_cnf_01.pdf|  Processor Shield for L1 Data Cache Software-Based On-line Self-testing}}, \\ //in Asia South Pacific Des. Autom. Conf.//  , \\ January 16-19, 2017, Japan \\ \\ 
-  - Tzu-Hsuan Hsu, Ching-Wen Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_cnf_02.pdf|Using Condition Flag Prediction to Improve the Performance of Out-of-Order Processors}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)//, \\ May 19-23, 2013 ,Beijing, China. \\ \\ +  - J.-W. Lin , and ____[[Member:Advisor|Chung-Ho Chen]]____,\\ {{research:caslab_2016_cnf_02.pdf| A Processor Shield for Software-Based On-Line Self-Test}}, \\ //in IEEE Asia Pacific Conf. Circuits and Systems//, \\ October 25-28, 2016, Korea \\ \\ 
-  - Chien-Te Liu, Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_cnf_01.pdf|CASL Hypervisor and its Virtualization Platform}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)//, \\ May 19-23, 2013 ,Beijing, China. \\ \\ +  - Yun-Chi Huang, Kuan-Chieh Hsu, Wan-shan Hsieh, Chen-Chieh Wang, Chia-Han Lu, and __[[Member:Advisor|Chung-Ho Chen]]___,\\ {{research:caslab_2016_cnf_01.pdf|Dynamic SIMD Re-convergence with Paired-Path Comparison }}  , \\ //in the 2016 IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 23-25, 2016, Montreal, Canada. \\ \\ 
-  - Hsu-Yao Huang, Chi-Yuan Huang, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|Tile-Based GPU Optimizations through ESL Full System Simulation}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 20-23, 2012, Seoul, Korea.  \\ \\+  - Yung Hsu and __ __[[Member:Advisor|Chung-Ho Chen]]____, \\ {{research:caslab_2015_cnf_02.pdf|A Heterogeneous System Architecture Conformed GPU Platform Supporting OpenCL and OpenGL}}, \\ //Taiwan and Japan Conference on Circuits and Systems (TJCAS)//, \\ Aug. 18-23, 2015, Japan \\ \\ 
 +  - Heng-Yi Chen,__ __ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{|An HSAIL ISA Conformed GPU Platform}}, \\ //In International Conference on Innovation, Communication and Engineering (ICICE)//, \\  Oct 23-28. 2015. Xiangtan, Hunan, P.R. China\\ \\ 
 +  - Chien-Hsuan Yen, Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2015_cnf_01.pdf|A memory-efficient NoC system for OpenCL many-core platform}}, \\ //in the 2015 IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 24-27, 2015, Lisbon, Portugal. \\ \\  
 +  - Ching-Wen Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_02.pdf|Unambiguous I-cache testing using software-based self-testing methodology}}, \\ //in the 2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ June 1-5, 2014 ,Melbourne VIC, Australian. \\ \\ 
 +  - Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_03.pdf|An OpenCL Runtime System for a Heterogeneous many-Core Virtual Platform }}, \\ //in the 2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ June 1-5, 2014 ,Melbourne VIC, Australian. \\ \\ 
 +  - __[[en:member:elvis|Jhe-Yu Liou]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_01.pdf|Re-visit Blocking Texture Cache Design for Modern GPU}}, \\ //in the 11th International SoC Design Conference (ISOCC)//, \\ Nov. 3-6, 2014, Jeju, Korea. \\ \\ 
 +  - Tzu-Hsuan Hsu, Ching-Wen Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_cnf_02.pdf|Using Condition Flag Prediction to Improve the Performance of Out-of-Order Processors}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 19-23, 2013 ,Beijing, China. \\ \\ 
 +  - Chien-Te Liu, Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_cnf_01.pdf|CASL Hypervisor and its Virtualization Platform}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 19-23, 2013 ,Beijing, China. \\ \\ 
 +  - Hsu-Yao Huang, Chi-Yuan Huang, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_01.pdf|Tile-Based GPU Optimizations through ESL Full System Simulation}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 20-23, 2012, Seoul, Korea.  \\ \\
   - __[[Member:jay|Chen-Chieh Wang]]__, Sheng-Hsin Lo, Yao-Ning Liu, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 20-23, 2012, Seoul, Korea.  \\ \\   - __[[Member:jay|Chen-Chieh Wang]]__, Sheng-Hsin Lo, Yao-Ning Liu, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, \\ May 20-23, 2012, Seoul, Korea.  \\ \\
   - __[[Member:jay|Chen-Chieh Wang]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ An Optimized Cryptographic Processing Unit for IPsec Processors, \\ //in the 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)//, \\ June 19-22, 2011, Gyeongju, Korea.  \\ \\   - __[[Member:jay|Chen-Chieh Wang]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ An Optimized Cryptographic Processing Unit for IPsec Processors, \\ //in the 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)//, \\ June 19-22, 2011, Gyeongju, Korea.  \\ \\
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