research:competition
多媒體管理器
分類名稱
選擇分類名稱
媒體檔案
在 course:logic_system 中的檔案
- 期末線上考試流程.pdf
- 2021/06/24 12:23
- 92.7 KB
- 2016邏設hw1成績v1.pdf
- 2016/06/02 08:55
- 153.3 KB
- lecture_1_outlines_and_numbers_2016.ppt
- 2016/02/24 11:35
- 1.5 MB
- lecture_2-1_boolean_algebra_2016.pdf
- 2016/02/25 06:59
- 301.2 KB
- lecture_2_boolean_algebra_basic.pdf
- 2016/02/25 06:59
- 144.8 KB
- lecture_3_algebraic_simplification.pdf
- 2016/02/25 06:59
- 84.8 KB
- lecture_4_minterm_and_maxterm.pdf
- 2016/02/25 06:59
- 236.5 KB
- lecture_5_karnaugh_maps.pdf
- 2016/02/25 06:59
- 1.2 MB
- lecture_6_quine-mccluskey_method.pdf
- 2016/02/25 06:59
- 629.9 KB
- lecture_7_multi-level_gate_networks.pdf
- 2016/02/25 06:59
- 1.9 MB
- lecture_8_combinational_network_design.pdf
- 2016/02/25 06:59
- 378.1 KB
- lecture_9_-b_mux-dmux_tree.pdf
- 2016/02/25 06:59
- 534.8 KB
- lecture_9_mux_decoder_rom_2016.pdf
- 2016/02/25 06:59
- 2 MB
- lecture_10_latch_and_flip-flop_2016.pdf
- 2016/02/25 06:59
- 1.3 MB
- lecture_11-1_fpgas_shannon.pdf
- 2016/02/25 06:59
- 876.1 KB
- lecture_11_registers_and_counters.pdf
- 2016/02/25 06:59
- 894 KB
- lecture_12_analysis_of_clocked_sequential_network.pdf
- 2016/02/25 06:59
- 764 KB
- lecture_13_derivation_of_state_graphs_and_tables.pdf
- 2016/02/25 06:59
- 1.6 MB
- lecture_14_reduction_of_state_tables.pdf
- 2016/02/25 06:59
- 1.6 MB
- lecture_15_sequential_circuit_design.pdf
- 2016/02/25 06:59
- 1.1 MB
- lecture_16_circuits_for_arithmetic_operations.pdf
- 2016/02/25 06:59
- 444.7 KB
- lecture_17_state_machine_charts.pdf
- 2016/02/25 06:59
- 789.9 KB
- lecture_adder_mutiplier_circuit_cla.ppt
- 2016/02/26 02:45
- 823.5 KB
- logic2016grade_mid1.png
- 579×288
- 2016/04/29 16:39
- 8 KB
- logic2016grade_mid2.png
- 480×289
- 2016/06/13 13:51
- 7.1 KB
- logic_final_locked.pdf
- 2021/06/24 12:26
- 908 KB
- logic_system_assignment_2_2020sprig1.pdf
- 2020/05/26 23:23
- 367.2 KB
- supplement_on_verilog_for_asm_chart.pptx
- 2016/02/26 02:45
- 66.1 KB
- supplement_on_verilog_with_adder_examples.pptx
- 2016/02/26 02:45
- 134.4 KB
- supplement_on_verilog_with_adder_examples_3-28.pptx
- 2016/02/26 02:45
- 595.7 KB
- supplement_on_verilog_with_com_ckt_examples.pptx
- 2016/02/26 02:45
- 173.6 KB
- supplement_on_verilog_with_ff_examples.pptx
- 2016/02/26 02:45
- 237.4 KB
- supplement_on_verilog_with_sequential_circuits_examples_fsm.pptx
- 2016/02/26 02:45
- 586 KB
research/competition.txt · 上一次變更: 2014/11/22 15:05 由 elvis
若無特別註明，本 wiki 上的內容都是採用以下授權方式： CC Attribution-Share Alike 4.0 International
