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 ===== Journal ===== ===== Journal =====
----------------------------------- +  - __En-Hao Chang__, __[[Member:jay|Chen-Chieh Wang]]__, __Chien-Te Liu__, __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_jnl_01.pdf|Virtualization Technology for TCP/IP Offload Engine}}, \\ //IEEE Transactions on Cloud Computing//, \\ Vol. 2, No. 2, April-June 2014. **(SCI, EI)** \\ \\
-  - __En-Hao Chang__, __[[Member:jay|Chen-Chieh Wang]]__, __Chien-Te Liu__, __[[Member:edi|Kuan-Chung Chen]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_jnl_01.pdf|Virtualization Technology for TCP/IP Offload Engine}}, \\ //IEEE Transactions on Cloud Computing//, Vol. 2, No. 2, April-June 2014. **(SCI, EI)** \\ \\+
   - __[[Member:jay|Chen-Chieh Wang]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_jnl_01.pdf|A System‐Level Network Virtual Platform for IPsec Processor Development}}, \\ //IEICE Transactions on Information and Systems//, \\ Vol.E96-D, No.5, pp.1095-1104, May 2013. **(SCI, EI)**  \\ \\   - __[[Member:jay|Chen-Chieh Wang]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_jnl_01.pdf|A System‐Level Network Virtual Platform for IPsec Processor Development}}, \\ //IEICE Transactions on Information and Systems//, \\ Vol.E96-D, No.5, pp.1095-1104, May 2013. **(SCI, EI)**  \\ \\
-  - __Yi-Ying Tsai__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2011_jnl_02.pdf|Energy-efficient Trace Reuse Cache for Embedded Processor}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 19, No. 9, pp. 1681-1694, September 2011. **(SCI, EI)**  \\ \\ +  - __Yi-Ying Tsai__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2011_jnl_02.pdf|Energy-efficient Trace Reuse Cache for Embedded Processor}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 19, No. 9, pp. 1681-1694, September 2011. **(SCI, EI)**  \\ \\ 
-  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2011_jnl_01.pdf|Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 19, No. 3, pp. 516-520, March 2011. **(SCI, EI)**  \\ \\ +  - Tai-Hua Lu, __[[Member:Advisor|Chung-Ho Chen]]__, and Kuen-Jong Lee, \\ {{research:caslab_2011_jnl_01.pdf|Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 19, No. 3, pp. 516-520, March 2011. **(SCI, EI)**  \\ \\ 
-  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_02.pdf|Frame Buffer Access Reduction for MPEG Video Decoder}}, \\ //IEEE Transactions on Circuits and Systems for Video Technology//, Vol. 18, No. 10, pp. 1452-1456, October 2008. **(SCI, EI)**  \\ \\ +  - Wei-Cheng Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_02.pdf|Frame Buffer Access Reduction for MPEG Video Decoder}}, \\ //IEEE Transactions on Circuits and Systems for Video Technology//, \\ Vol. 18, No. 10, pp. 1452-1456, October 2008. **(SCI, EI)**  \\ \\ 
-  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_01.pdf|Configurable VLSI Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 16, No. 8, pp. 1072-1082, August 2008. **(SCI, EI)**   \\ \\ +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2008_jnl_01.pdf|Configurable VLSI Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 16, No. 8, pp. 1072-1082, August 2008. **(SCI, EI)**   \\ \\ 
-  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ Window Architecture for Deblocking Filter in H.264/AVC, \\ //International Journal of Innovative Computing//, Information and Control, Vol. 3, No. 6, pp. 1677-1695, December 2007. **(SCI, EI)**  \\ \\ +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ Window Architecture for Deblocking Filter in H.264/AVC, \\ //International Journal of Innovative Computing//, Information and Control, \\ Vol. 3, No. 6, pp. 1677-1695, December 2007. **(SCI, EI)**  \\ \\ 
-  - __[[Member:Advisor|Chung-Ho Chen]]__ and Kuo-Su Hsiao, \\ {{research:caslab_2007_jnl_04.pdf|Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality}}, \\ IEEE Transactions on Computers, Vol. 56, No. 11, pp. 1534-1548, November 2007. **(SCI, EI)**  \\ \\ +  - __[[Member:Advisor|Chung-Ho Chen]]__ and Kuo-Su Hsiao, \\ {{research:caslab_2007_jnl_04.pdf|Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality}}, \\ //IEEE Transactions on Computers//, \\ Vol. 56, No. 11, pp. 1534-1548, November 2007. **(SCI, EI)**  \\ \\ 
-  - __[[Member:Advisor|Chung-Ho Chen]]__, Chao-Hsien Hsu, and __[[Member:jay|Chen-Chieh Wang]]__, \\ {{research:caslab_2007_jnl_03.pdf|Scalable IPv6 Lookup/Update Design for High-Throughput Routers}}, \\ //Journal of Internet Technology//, Vol. 8, No. 3, pp. 261-269, July 2007. **(EI)**  \\ \\ +  - __[[Member:Advisor|Chung-Ho Chen]]__, Chao-Hsien Hsu, and __[[Member:jay|Chen-Chieh Wang]]__, \\ {{research:caslab_2007_jnl_03.pdf|Scalable IPv6 Lookup/Update Design for High-Throughput Routers}}, \\ //Journal of Internet Technology//, \\ Vol. 8, No. 3, pp. 261-269, July 2007. **(EI)**  \\ \\ 
-  - __[[Member:Advisor|Chung-Ho Chen]]__, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao, \\ {{research:caslab_2007_jnl_02.pdf|Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 15, No. 5, pp. 505-517, May 2007. **(SCI, EI)**  \\ \\ +  - __[[Member:Advisor|Chung-Ho Chen]]__, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao, \\ {{research:caslab_2007_jnl_02.pdf|Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 15, No. 5, pp. 505-517, May 2007. **(SCI, EI)**  \\ \\ 
-  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2007_jnl_01.pdf|An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEICE Transactions on Information and Systems//, Vol. E90-D, No.1 pp.99-107, January 2007. **(SCI, EI)**  \\ \\ +  - Chung-Ming Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2007_jnl_01.pdf|An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC}}, \\ //IEICE Transactions on Information and Systems//, \\ Vol. E90-D, No.1 pp.99-107, January 2007. **(SCI, EI)**  \\ \\ 
-  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_jnl_01.pdf|Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, Vol. 14, No. 10, pp. 1089-1102, October 2006. **(SCI, EI)**  \\ \\ +  - Kuo-Su Hsiao and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2006_jnl_01.pdf|Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation}}, \\ //IEEE Transactions on Very Large Scale Integration Systems//, \\ Vol. 14, No. 10, pp. 1089-1102, October 2006. **(SCI, EI)**  \\ \\ 
-  - M.-D. Shieh, M.-H. Sheu, __[[Member:Advisor|C.-H. Chen]]__ , and H.-F. Lo, \\ {{research:caslab_2001_jnl_01.pdf|A Systematic Approach for Parallel CRC Computations}}, \\ //Journal of Information Science and Engineering//, Vol. 17, No. 3, pp. 445-461, May 2001. **(SCI)**  \\ \\ +  - M.-D. Shieh, M.-H. Sheu, __[[Member:Advisor|C.-H. Chen]]__ , and H.-F. Lo, \\ {{research:caslab_2001_jnl_01.pdf|A Systematic Approach for Parallel CRC Computations}}, \\ //Journal of Information Science and Engineering//, \\ Vol. 17, No. 3, pp. 445-461, May 2001. **(SCI)**  \\ \\ 
-  - __[[Member:Advisor|C.-H. Chen]]__ and Akida Wu, \\ Address Prediction Using a Bit-Matrix Indexing Scheme for Selective Update, \\ //Journal of Computers//, Vol. 12 No.3, September 2000.  \\ \\ +  - __[[Member:Advisor|C.-H. Chen]]__ and Akida Wu, \\ Address Prediction Using a Bit-Matrix Indexing Scheme for Selective Update, \\ //Journal of Computers//, \\ Vol. 12 No.3, September 2000.  \\ \\ 
-  - __[[Member:Advisor|C.-H. Chen]]__ and Akida Wu, \\ Performance Evaluation of Load/Store Issue and Memory Access Policies, \\ //Journal of the Chinese Institute of Engineers//, Vol.23, No. 6, pp. 697-709, 2000. **(SCI, EI)**+  - __[[Member:Advisor|C.-H. Chen]]__ and Akida Wu, \\ Performance Evaluation of Load/Store Issue and Memory Access Policies, \\ //Journal of the Chinese Institute of Engineers//, \\ Vol.23, No. 6, pp. 697-709, 2000. **(SCI, EI)**
  
 \\ \\
 ===== Conference ===== ===== Conference =====
-------------------- 
   - __[[en:member:elvis|Jhe-Yu Liou]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_01.pdf|Re-visit Blocking Texture Cache Design for Modern GPU}}, \\ //in the 11th International SoC Design Conference (ISOCC)//, \\ Nov. 3-6, 2014, Jeju, Korea. \\ \\   - __[[en:member:elvis|Jhe-Yu Liou]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2014_cnf_01.pdf|Re-visit Blocking Texture Cache Design for Modern GPU}}, \\ //in the 11th International SoC Design Conference (ISOCC)//, \\ Nov. 3-6, 2014, Jeju, Korea. \\ \\
   - Tzu-Hsuan Hsu, Ching-Wen Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_cnf_02.pdf|Using Condition Flag Prediction to Improve the Performance of Out-of-Order Processors}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)//, May 19-23, 2013 ,National Cheng Kung University, Tainan, Taiwan  \\ \\   - Tzu-Hsuan Hsu, Ching-Wen Lin and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_cnf_02.pdf|Using Condition Flag Prediction to Improve the Performance of Out-of-Order Processors}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)//, May 19-23, 2013 ,National Cheng Kung University, Tainan, Taiwan  \\ \\
   - Chien-Te Liu, Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_cnf_01.pdf|CASL Hypervisor and its Virtualization Platform}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)//, May 19-23, 2013 ,National Cheng Kung University, Tainan, Taiwan  \\ \\   - Chien-Te Liu, Kuan-Chung Chen and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2013_cnf_01.pdf|CASL Hypervisor and its Virtualization Platform}}, \\ //in the IEEE International Symposium on Circuits and Syatem(ISCAS)//, May 19-23, 2013 ,National Cheng Kung University, Tainan, Taiwan  \\ \\
-  - Hsu-Yao Huang, Chi-Yuan Huang, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|Tile-Based GPU Optimizations through ESL Full System Simulation}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, May 20-23, 2012, Seoul, Korea.  \\ \\+  - Hsu-Yao Huang, Chi-Yuan Huang, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_01.pdf|Tile-Based GPU Optimizations through ESL Full System Simulation}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, May 20-23, 2012, Seoul, Korea.  \\ \\
   - __[[Member:jay|Chen-Chieh Wang]]__, Sheng-Hsin Lo, Yao-Ning Liu, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, May 20-23, 2012, Seoul, Korea.  \\ \\   - __[[Member:jay|Chen-Chieh Wang]]__, Sheng-Hsin Lo, Yao-Ning Liu, and __[[Member:Advisor|Chung-Ho Chen]]__, \\ {{research:caslab_2012_cnf_02.pdf|NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development}}, \\ //in the IEEE International Symposium on Circuits and Systems (ISCAS)//, May 20-23, 2012, Seoul, Korea.  \\ \\
   - __[[Member:jay|Chen-Chieh Wang]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ An Optimized Cryptographic Processing Unit for IPsec Processors, \\ //in the 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)//, June 19-22, 2011, Gyeongju, Korea.  \\ \\   - __[[Member:jay|Chen-Chieh Wang]]__ and __[[Member:Advisor|Chung-Ho Chen]]__, \\ An Optimized Cryptographic Processing Unit for IPsec Processors, \\ //in the 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)//, June 19-22, 2011, Gyeongju, Korea.  \\ \\
en/research/publication.1415954979.txt.gz · Last modified: 2014/11/14 08:49 by elvis

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