計算機架構與系統實驗室

Computer Architecture and System Laboratory

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edu_project:cpucourse

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Both sides previous revision 前次修改
下次修改 		前次修改
edu_project:cpucourse [2014/10/06 15:28]
elvis [課程資訊] 		edu_project:cpucourse [2016/10/05 08:26] (目前版本)
a2215689
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 \\ \\
 ===== 課程資訊 ====== ===== 課程資訊 ======
----- 
  
  
-^ Instructor  |[[member:advisor|陳中和]]  教授 | +^ Instructor  | [[member:advisor|陳中和]]  教授                                                                                                                             | 
-^  \\ TA  | 徐　鏞<csh01279@gmail.com> \\ 齊　元<jimbochi47@gmail.com> \\ 謝宛珊<vanaheim.wen@gmail.com> \\ 許冠傑<jk78346@gmail.com> |+^  \\ TA      | 曾柏翔<an4001022@gmail.com> \\ 張瑞元<ray.chang925@gmail.com> \\ 邱健鳴<arnoishandsome@gmail.com> \\ 許元杰<opudding7654321@gmail.com> \\ 蔡森至<a2215689@gmail.com> \\ ( [[Course:co:104|2015計算機組織]]) |
  
 \\ \\
 ===== 講義與實驗教材下載 ===== ===== 講義與實驗教材下載 =====
----- +  * {{:edu_project:cpulab_1.pdf |LAB  01: Get to know the whole MIPS and C2A}} 
-<wrap hi info> 如果需要投影片密碼請寄信聯絡[[member:advisor|陳中和老師]]</wrap> \\ +  * {{:edu_project:cpulab_2.pdf |LAB  02: Find out how to translate the C code to Assembly code}} 
-{{:edu_project:cpulab_1.pdf |LAB 01：Get to know the whole MIPS and C2A}} \\ +  * {{:edu_project:cpulab_3.pdf |LAB  03: SystemC Implementation Of Instruction Function}} 
-{{:edu_project:cpulab_2.pdf |LAB 02: Find out how to translate the C code to Assembly code}} \\ +  * {{:edu_project:cpulab_4.pdf |LAB  04: Verilog Implementation Of Instruction Function}} 
-{{:edu_project:cpulab_3.pdf |LAB 03: SystemC Implementation Of Instruction Function}} \\ +  * {{:edu_project:cpulab_5.pdf |LAB  05: Verilog Implementation Of Arithmetic Logic Unit}} 
-{{:edu_project:cpulab_4.pdf |LAB 04: Verilog Implementation Of Instruction Function}} \\ +  * {{:edu_project:cpulab_6.pdf |LAB  06: Verilog Implementation Of I-Cache}} 
-{{:edu_project:cpulab_5.pdf |LAB 05: Verilog Implementation Of Arithmetic Logic Unit}} \\ +  * {{:edu_project:cpulab_7.pdf |LAB  07: Set-Associative D-cache}} 
-{{:edu_project:cpulab_6.pdf |LAB 06: Verilog Implementation Of I-Cache}} \\ +  * {{:edu_project:cpulab_8.pdf |LAB  08: Introduction to a simple CPU system platform & Memory Allocation}} 
-{{:edu_project:cpulab_7.pdf |LAB 07: Set-Associative D-cache}} \\ +  * {{:edu_project:cpulab_9.pdf |LAB  09: Introduction to a simple Multi-Master Bus Platform & Generic I/Os}} 
-{{:edu_project:cpulab_8.pdf |LAB 08: Introduction to a simple CPU system platform & Memory Allocation}} \\ +  * {{:edu_project:cpulab_10.pdf |LAB 10: Introduction to Interrupt Controller & Interrupt Service Routines on EASY Platform}} 
-{{:edu_project:cpulab_9.pdf |LAB 09:  Introduction to a simple Multi-Master Bus Platform & Generic I/ Os}} \\ +  * {{:edu_project:cpulab_solution.rar|LAB01-10(Files and Solutions)}} 
-{{:edu_project:cpulab_10.pdf |LAB 10:   Introduction to Interrupt Controller & Interrupt Service Routines on EASY Platform}} \\ +<WRAP info round 60%> 如需投影片密碼請寄信聯絡[[member:advisor|陳中和老師]]</WRAP>
-{{:edu_project:cpulab_solution.rar|LAB01-10(Files and Solutions)}} \\+
  
  
 +----
 +
 +~~DISQUS~~
  
  
  
edu_project/cpucourse.1412609300.txt.gz · 上一次變更: 2014/11/10 02:36 (外部編輯)

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