差異處

這裏顯示兩個版本的差異處。

--- course:logic_system_practice:110 [2022/03/06 09:30]
admin
+++ course:logic_system_practice:110 [2022/05/10 01:51] (目前版本)
admin
@@ 行 23: / 行 23: @@
   * {{:course:logic_system_practice:02_laboratory_2.pdf|Lab 2 - 基本邏輯閘應用}}
   * {{:course:logic_system_practice:03_laboratory-3.pdf|Lab 3 - 半加器與全加器實作}}
+  * {{:course:logic_system_practice:04_laboratory-4.pdf|Lab 4 - Xilinx Vivado 介紹 & Verilog 簡介}}
+  * {{:course:logic_system_practice:05_laboratory_5.pdf|Lab 5 - Verilog - Combinational Design}}
+  * {{:course:logic_system_practice:06_laboratory_6.pdf|Lab 6 - Verilog - Sequential Design(1)}}
+  * {{:course:logic_system_practice:07_laboratory-7.pdf|Lab 7 - Verilog - Sequential Design(2)}}
+  * {{:course:logic_system_practice:08_laboratory-8.pdf|Lab 8 - Verilog - Sequential Design(3)}}
+  * {{:course:logic_system_practice:09_laboratory-9.pptx|Lab 9 - Pynq 與七段顯示器}}
+  * {{:course:logic_system_practice:pynq_op.pptx|Pynq 操作補充}}
+  * {{:course:logic_system_practice:10_laboratory-10.pptx|Lab 10 - Pynq 呼吸燈}}
+===== 實驗檔案下載 =====
+  * {{:course:logic_system_practice:lab4.zip|Lab 4 - 實驗檔案}}
+  * {{:course:logic_system_practice:lab5_for_student.zip|Lab 5 - 實驗檔案}}
+  * {{:course:logic_system_practice:lab6.zip|Lab 6 - 實驗檔案}}
+  * {{:course:logic_system_practice:lab7.zip|Lab 7 - 實驗檔案}}
+  * {{:course:logic_system_practice:lab8.zip|Lab 8 - 實驗檔案}}
+  * {{:course:logic_system_practice:lab9.zip|Lab 9 - 實驗檔案}}
+  * {{:course:logic_system_practice:lab10.zip|Lab 10 - 實驗檔案}}
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