EASY Project Status (12/20/2012 - 22:04:40) | |||
Project File: | fuct.xise | Parser Errors: | No Errors |
Module Name: | EASY | Implementation State: | Programming File Generated |
Target Device: | xc5vlx110t-1ff1136 |
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No Errors |
Product Version: | ISE 13.2 |
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143 Warnings (0 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Slice Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Registers | 574 | 69,120 | 1% | ||
Number used as Flip Flops | 573 | ||||
Number used as Latches | 1 | ||||
Number of Slice LUTs | 531 | 69,120 | 1% | ||
Number used as logic | 339 | 69,120 | 1% | ||
Number using O6 output only | 284 | ||||
Number using O5 output only | 51 | ||||
Number using O5 and O6 | 4 | ||||
Number used as Memory | 183 | 17,920 | 1% | ||
Number used as Dual Port RAM | 8 | ||||
Number using O5 and O6 | 8 | ||||
Number used as Single Port RAM | 18 | ||||
Number using O6 output only | 18 | ||||
Number used as Shift Register | 157 | ||||
Number using O6 output only | 155 | ||||
Number using O5 output only | 1 | ||||
Number using O5 and O6 | 1 | ||||
Number used as exclusive route-thru | 9 | ||||
Number of route-thrus | 69 | ||||
Number using O6 output only | 60 | ||||
Number using O5 output only | 9 | ||||
Number of occupied Slices | 318 | 17,280 | 1% | ||
Number of LUT Flip Flop pairs used | 798 | ||||
Number with an unused Flip Flop | 224 | 798 | 28% | ||
Number with an unused LUT | 267 | 798 | 33% | ||
Number of fully used LUT-FF pairs | 307 | 798 | 38% | ||
Number of unique control sets | 90 | ||||
Number of slice register sites lost to control set restrictions |
178 | 69,120 | 1% | ||
Number of bonded IOBs | 10 | 640 | 1% | ||
Number of LOCed IOBs | 10 | 10 | 100% | ||
Number of BlockRAM/FIFO | 3 | 148 | 2% | ||
Number using BlockRAM only | 3 | ||||
Number of 36k BlockRAM used | 1 | ||||
Number of 18k BlockRAM used | 2 | ||||
Total Memory used (KB) | 72 | 5,328 | 1% | ||
Number of BUFG/BUFGCTRLs | 3 | 32 | 9% | ||
Number used as BUFGs | 3 | ||||
Number of BSCANs | 1 | 4 | 25% | ||
Number of DCM_ADVs | 1 | 12 | 8% | ||
Number of RPM macros | 9 | ||||
Average Fanout of Non-Clock Nets | 3.00 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | 週四 十二月 20 22:02:15 2012 | 0 | 136 Warnings (0 new) | 3 Infos (0 new) | |
Translation Report | Current | 週四 十二月 20 22:02:43 2012 | 0 | 1 Warning (0 new) | 0 | |
Map Report | Current | 週四 十二月 20 22:03:16 2012 | 0 | 5 Warnings (0 new) | 8 Infos (0 new) | |
Place and Route Report | Current | 週四 十二月 20 22:03:47 2012 | 0 | 0 | 1 Info (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | 週四 十二月 20 22:04:00 2012 | 0 | 0 | 2 Infos (0 new) | |
Bitgen Report | Current | 週四 十二月 20 22:04:31 2012 | 0 | 1 Warning (0 new) | 2 Infos (0 new) |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | 週四 十二月 20 22:04:32 2012 | |
WebTalk Log File | Current | 週四 十二月 20 22:04:39 2012 |