EASY Project Status (12/20/2012 - 20:18:06) | |||
Project File: | fuct.xise | Parser Errors: | No Errors |
Module Name: | my_dcm | Implementation State: | Programming File Not Generated |
Target Device: | xc5vlx110t-1ff1136 |
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Product Version: | ISE 13.2 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | 週四 十二月 20 20:17:59 2012 | |
WebTalk Log File | Current | 週四 十二月 20 20:18:05 2012 |