EASY Project Status
Project File: fuct.xise Parser Errors: No Errors
Module Name: EASY Implementation State: New
Target Device: xc5vlx110t-1ff1136
  • Errors:
No Errors
Product Version:ISE 13.2
  • Warnings:
851 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 7,009 69,120 10%  
    Number used as Flip Flops 6,997      
    Number used as Latches 10      
    Number used as Latch-thrus 2      
Number of Slice LUTs 11,153 69,120 16%  
    Number used as logic 10,653 69,120 15%  
        Number using O6 output only 10,157      
        Number using O5 output only 208      
        Number using O5 and O6 288      
    Number used as Memory 482 17,920 2%  
        Number used as Dual Port RAM 193      
            Number using O6 output only 141      
            Number using O5 output only 2      
            Number using O5 and O6 50      
        Number used as Shift Register 289      
            Number using O6 output only 287      
            Number using O5 output only 1      
            Number using O5 and O6 1      
    Number used as exclusive route-thru 18      
Number of route-thrus 322      
    Number using O6 output only 223      
    Number using O5 output only 96      
    Number using O5 and O6 3      
Number of occupied Slices 5,119 17,280 29%  
Number of LUT Flip Flop pairs used 14,400      
    Number with an unused Flip Flop 7,391 14,400 51%  
    Number with an unused LUT 3,247 14,400 22%  
    Number of fully used LUT-FF pairs 3,762 14,400 26%  
    Number of unique control sets 490      
    Number of slice register sites lost
        to control set restrictions
684 69,120 1%  
Number of bonded IOBs 12 640 1%  
    Number of LOCed IOBs 12 12 100%  
    IOB Latches 7      
Number of BlockRAM/FIFO 37 148 25%  
    Number using BlockRAM only 37      
        Number of 36k BlockRAM used 36      
        Number of 18k BlockRAM used 1      
    Total Memory used (KB) 1,314 5,328 24%  
Number of BUFG/BUFGCTRLs 4 32 12%  
    Number used as BUFGs 4      
Number of BSCANs 1 4 25%  
Number of DCM_ADVs 1 12 8%  
Number of DSP48Es 4 64 6%  
Number of RPM macros 9      
Average Fanout of Non-Clock Nets 4.67      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent週二 十二月 11 18:11:30 20120762 Warnings (0 new)94 Infos (0 new)
Translation ReportCurrent週二 十二月 11 18:12:05 201201 Warning (0 new)0
Map ReportCurrent週二 十二月 11 18:14:07 2012083 Warnings (0 new)9 Infos (0 new)
Place and Route ReportCurrent週二 十二月 11 18:15:35 201203 Warnings (0 new)1 Info (0 new)
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrent週二 十二月 11 18:15:58 2012002 Infos (0 new)
Bitgen ReportCurrent週二 十二月 11 18:17:18 201202 Warnings (0 new)2 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent週二 十二月 11 18:17:21 2012
WebTalk Log FileCurrent週二 十二月 11 18:17:28 2012

Date Generated: 12/11