====== 邏輯系統 (109 Spring) ====== 109學年度第2學期邏輯系統 \\ \\ \\ \\ ===== 最新消息 ===== |< 100% 20% 80% >| ^ 02/22 | 開學快樂 | ^ 02/26 | :!:需要加簽的同學,請於星期五2/26上課前 （13:00-13:10 pm）,提早到上課教室找助教登記,由於加簽人數過多,會以現場抽籤方式決定7位可加簽者（p.s.可加簽人數為10%,即7位）:!:| ^ 03/05 | 停課一次 | ^ 03/16 | 晚上18:10~20:00補課 | ^ 03/26 | 邏輯系統第一次作業公佈：\\ {{course:logic_system:ls109b:logic_system_assignment1.pdf|2021 Logic System Assignment 1 - K-map}}\\ 繳交期限： 04/16 (五)前，上傳方式為ftp，詳見Assignment。\\ | ^ 04/09 | 第一次期中考（第一章到第六章） | ^ 04/16 | 11:59:59pm 第一次作業繳交截止 | ^ 04/21 | 停課一次 | ^ 04/27 | 晚上18:00~20:00補課 | ^ 05/07 | 邏輯系統第二次作業公佈：\\ {{course:logic_system:ls109b:logic_system_assignment2.pdf|2021 Logic System Assignment 2 - Quine-McCluskey}}\\ 繳交期限： 06/11 (五)前，上傳方式為ftp，詳見Assignment。\\ | ^ 05/14 | 第二次期中考（範圍第七章～第十章） | ===== 課程資訊 ===== ^ Instructor | [[:member:advisor|陳中和 教授]] | ^ \\ TA | 林聖堯 \\ 王祥宇 \\ 羅子渝 \\ 謝承佑 \\ 周欣玄 \\ 李昱樺 | ^ Classroom | 92185, EE Department Building | ^ Course Time | Wed 8:10 ~ 9:00 \\ Fri 13:10~15:00 | ^ Textbook | 自編講義 | ^ Grading | Examinations (3 Quizzes) \\ Homework | \\ ===== 上課講義 ===== * {{course:logic_system:ls106b:lecture_1_outlines_and_numbers.ppt]] |Lecture 1 Outlines and Numbers }} * {{course:logic_system:ls106b:lecture_2_boolean_algebra_basic.ppt]] |Lecture 2 Boolean Algebra Basic}} * {{course:logic_system:ls106b:lecture_2-1_boolean_algebra.ppt]] |Lecture 2-1 Boolean Algebra}} * {{course:logic_system:ls106b:lecture_3_algebraic_simplification.ppt]] |Lecture 3 Algebraic Simplification}} * {{course:logic_system:ls106b:lecture_4_minterm_and_maxterm.ppt]] |Lecture 4 Minterm and Maxterm}} * {{course:logic_system:ls106b:lecture_5_karnaugh_maps.ppt]] |Lecture 5 Karnaugh maps}} * {{course:logic_system:ls106b:lecture_6_quine-mccluskey_method.ppt]] |Lecture 6 Quine-McCluskey Method}} * {{course:logic_system:ls106b:lecture_7_multi-level_gate_networks.ppt]] |Lecture 7 Multi-Level Gate Networks}} * {{course:logic_system:ls106b:lecture_8_combinational_network_design.ppt]] |Lecture 8 Combinational network design}} * {{course:logic_system:ls106b:lecture_9_-b_mux-dmux_tree.ppt]] |Lecture 9-B MUX-DMUX Tree}} * {{course:logic_system:ls106b:lecture_9_mux_decoder_rom.ppt]] |Lecture 9 Mux Decoder ROM}} * {{course:logic_system:ls106b:lecture_10_latch_and_flip-flop.ppt]] |Lecture 10 Latch and Flip-flop}} * {{course:logic_system:ls106b:lecture_11_registers_and_counters.ppt]] |Lecture 11 Registers and Counters}} * {{course:logic_system:ls106b:lecture_11-1_fpgas_shannon.pptx]] |Lecture 11-1 FPGAs Shannon}} * {{course:logic_system:ls106b:lecture_12_analysis_of_clocked_sequential_network.ppt]] |Lecture 12 Analysis of Clocked sequential network}} * {{course:logic_system:ls106b:lecture_13_derivation_of_state_graphs_and_tables.ppt]] |Lecture 13 Derivation of State Graphs and Tables}} * {{course:logic_system:ls106b:lecture_14_reduction_of_state_tables.ppt]] |Lecture 14 Reduction of State Tables}} * {{course:logic_system:ls106b:lecture_15_sequential_circuit_design.ppt]] |Lecture 15 Sequential circuit design}} * {{course:logic_system:ls106b:lecture_16_circuits_for_arithmetic_operations.ppt]] |Lecture 16 Circuits for Arithmetic Operations}} * {{course:logic_system:ls106b:lecture_17_state_machine_charts.ppt]] |Lecture 17 State Machine Charts}} ===== 補充資料 ===== * {{course:logic_system:ls106b:sub:lecture_2_supplement_verilog.pptx|Lecture 2 Supplement, Verilog}} * {{course:logic_system:ls106b:sub:lecture_supplement_adder_mutiplier.ppt|Adder Multiplier Circuit}} * {{course:logic_system:ls106b:sub:lecture_adder_mutiplier_circuit_cla.ppt]] |Adder Mutiplier Circuit CLA}} * {{course:logic_system:ls106b:sub:supplement_on_verilog_for_asm_chart.pptx]] |Supplement on verilog for ASM chart}} * {{course:logic_system:ls106b:sub:supplement_on_verilog_with_com_ckt_examples.pptx]] |Supplement on verilog with com ckt examples}} * {{course:logic_system:ls106b:sub:supplement_on_verilog_with_ff_examples.pptx]] |Supplement on verilog with FF examples}} * {{course:logic_system:ls106b:sub:supplement_on_verilog_with_sequential_circuits_examples_fsm.pptx]] |Supplement on verilog with sequential circuits examples, FSM}} * {{course:logic_system:ls106b:sub:supplement_on_verilog_with_adder_examples_3-28.pptx]] |Supplement on verilog with adder examples 3-28}} * {{course:logic_system:ls106b:sub:supplement_on_verilog_with_adder_examples.pptx]] |Supplement on verilog with adder examples}} * {{course:logic_system:ls106b:sub:multiplication_and_division.pptx]] |Multiplication and Division basics }} * {{course:logic_system:期末線上考試流程.pdf]] |期末考線上考試流程 }} * {{course:logic_system:logic_final_locked.pdf]] |logic_final_locked.pdf }} {{tabinclude>tab:research|研究成果, tab:group|研究群組, tab:member|實驗室成員 , tab:course|課程}} ~~DISQUS~~