Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthCaseImplStyle=Full |
PROP_SynthFsmEncode=None |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2012-08-23T10:47:15 |
PROP_intWbtProjectID=6818119734E24747968B95D02FE30FDE |
PROP_intWbtProjectIteration=106 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_AutoTop=true |
PROP_DevFamily=Virtex5 |
PROP_DevDevice=xc5vlx110t |
PROP_DevFamilyPMName=virtex5 |
PROP_DevPackage=ff1136 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-1 |
PROP_PreferredLanguage=Verilog |
FILE_CDC=1 |
FILE_COREGEN=1 |
FILE_NGC=1 |
FILE_UCF=1 |
FILE_VERILOG=27 |
FILE_XAW=1 |