EASY Project Status (01/06/2013 - 21:42:05)
Project File: fuct.xise Parser Errors: No Errors
Module Name: EASY Implementation State: Programming File Generated
Target Device: xc5vlx110t-1ff1136
  • Errors:
No Errors
Product Version:ISE 13.2
  • Warnings:
1096 Warnings (720 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 7,847 69,120 11%  
    Number used as Flip Flops 7,844      
    Number used as Latches 1      
    Number used as Latch-thrus 2      
Number of Slice LUTs 11,982 69,120 17%  
    Number used as logic 11,279 69,120 16%  
        Number using O6 output only 10,686      
        Number using O5 output only 243      
        Number using O5 and O6 350      
    Number used as Memory 674 17,920 3%  
        Number used as Dual Port RAM 201      
            Number using O6 output only 141      
            Number using O5 output only 2      
            Number using O5 and O6 58      
        Number used as Single Port RAM 18      
            Number using O6 output only 18      
        Number used as Shift Register 455      
            Number using O6 output only 453      
            Number using O5 output only 1      
            Number using O5 and O6 1      
    Number used as exclusive route-thru 29      
Number of route-thrus 374      
    Number using O6 output only 269      
    Number using O5 output only 102      
    Number using O5 and O6 3      
Number of occupied Slices 5,225 17,280 30%  
Number of LUT Flip Flop pairs used 15,442      
    Number with an unused Flip Flop 7,595 15,442 49%  
    Number with an unused LUT 3,460 15,442 22%  
    Number of fully used LUT-FF pairs 4,387 15,442 28%  
    Number of unique control sets 573      
    Number of slice register sites lost
        to control set restrictions
862 69,120 1%  
Number of bonded IOBs 14 640 2%  
    Number of LOCed IOBs 14 14 100%  
Number of BlockRAM/FIFO 40 148 27%  
    Number using BlockRAM only 40      
        Number of 36k BlockRAM used 39      
        Number of 18k BlockRAM used 1      
    Total Memory used (KB) 1,422 5,328 26%  
Number of BUFG/BUFGCTRLs 4 32 12%  
    Number used as BUFGs 4      
Number of BSCANs 1 4 25%  
Number of DCM_ADVs 1 12 8%  
Number of DSP48Es 4 64 6%  
Number of RPM macros 9      
Average Fanout of Non-Clock Nets 4.54      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent週日 一月 6 21:34:03 201301002 Warnings (720 new)100 Infos (53 new)
Translation ReportCurrent週日 一月 6 21:36:34 2013000
Map ReportCurrent週日 一月 6 21:38:33 2013093 Warnings (0 new)9 Infos (0 new)
Place and Route ReportCurrent週日 一月 6 21:40:02 2013001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrent週日 一月 6 21:40:26 2013002 Infos (0 new)
Bitgen ReportCurrent週日 一月 6 21:41:56 201301 Warning (0 new)2 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of Date週日 一月 6 21:41:57 2013
WebTalk Log FileOut of Date週日 一月 6 21:42:05 2013

Date Generated: 01/06/2013 -